Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Abstract: An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generates PWM control signals for controlling operation of the first and second transistors. The control signals are generated responsive to source PWM signals processed through programmable delay timers to generate set/reset control signals which set an output PWM control signal duty cycle.

Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

Abstract: A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range.

Abstract: In BLDC motors driven via sensorless techniques, the BEMF signals in the motor coils may be used to detect the position of the motor such that speed of the motor may be accurately controlled. When detecting the BEMF signals, however, small perturbations occur which negatively impact the rotational torque of the motor. As a result, torque ripple may occur at regular intervals which may result in inefficiencies as well as audible noise. In various embodiments as described herein, the sampling of the BEMF signals may be done so at pseudo-random intervals such that the overall spectral energy that presents from the BEMF detections may be reduced at specific frequencies (such as fundamental sampling frequencies and harmonics thereof) and spread out over many more frequencies. Thus, despite the overall spectral energy being the same, the amplitude of any given frequency is lower as the sampling of the BEMF is less periodic.

Abstract: The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit.

Abstract: An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

Abstract: An embodiment of an integrated scanner apparatus, includes a support surface for objects to be scanned, a scanner unit to perform a scanning movement relative to the support surface to capture images of portions of objects to be scanned, and a printer unit carried by a carriage mobile with respect to said support surface, wherein said scanner unit is carried by said carriage carrying said printer unit to be imparted said scanning movement by said carriage.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: An embodiment is a circuit for use with a display device, the circuit including: a first input node configured to be operatively coupled to a first port of a data source device that provides the display device with data, to receive a first direct voltage used for a real-time display of the data on the display device; and at least one output node, configured to operatively provide the display device with at least one output voltage generated based on the first direct voltage, wherein the first port is isolated from a data port used to transmit the data.

Abstract: In accordance with an embodiment, a method of operating a node coupled to a power network and a communications link includes receiving a status from a further node coupled to the power network via the communications link, and adjusting a power consumption of a device coupled to the node and powered by the power network based on the status message and based on a first rule set.

Abstract: A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.

Abstract: A method of performing a cryptographic operation including: receiving a plurality of binary input values; splitting the binary input values into a plurality of non-binary digits of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit) of base r.

Abstract: A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.

Abstract: An embodiment of method is described for controlling a voltage regulator of the type comprising at least one modulator of the PWM type, the method comprising: 1) generation of a control voltage signal for said PWM modulator; 2) frequency modulation of said control voltage signal obtaining a modulated control voltage signal having an harmonic at a switching frequency of said voltage regulator of reduced entity with respect to said control voltage signal; and 3) application of said modulated control voltage signal to said PWM modulator for generating a driving signal for said voltage regulator.

Abstract: The protected method of cryptographic computation includes N computation rounds successively performed to produce an output data from an input data and a private key. The method also includes a first masking stage to mask the input data, so that each intermediate data used or produced by a computation round is masked, and a second masking stage to mask data manipulated inside each computation round.