Abstract: A method comprising: a) during at least part of a conduction phase of the triac, measuring the gate potential of the triac; and b) comparing a value based on said measurement with a reference threshold and deducing the presence or the absence of an overcurrent based on said comparison.

Abstract: A system for processing a received signal having at least one code applied thereto, the received signal having a frequency, the system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein the first code and the second code are different; and processor for processing together the outputs of the first and second correlator circuitry to cancel the frequency.

Abstract: A method is provided for navigation of a mobile device. Spatial information of at least one beacon detected in an image relative to the image is determined. The image includes an image of the at least one beacon within at least part of an environment surrounding the mobile device. A position of the mobile device based on said spatial information is determined using encoded visual information of the at least one beacon.

Abstract: Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas.

Abstract: A data medium of the compact disc type may include medium areas of different types configured to define digital content, and a controllable element having two different states corresponding respectively to the two different types of areas. The controllable element may be configured to take selectively one of its states in response to a command, so as to modify in a controllable manner the content of the data medium.

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.

Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.

Abstract: A WLAN communication system and algorithm that adaptively changes the data transmission rate of a communication channel based on changing channel conditions. The WLAN communication system or algorithm has two modes being a searching mode and a transmission mode. Furthermore, the WLAN communication system or algorithm incorporates an additive increase, multiplicative decrease (AIMD) function into the rate adaptation algorithm.

Abstract: An electronic circuit includes several (at least two) oscillating and/or resonant devices. The circuit uses a measuring device to measure the phase noise of one of the two oscillating/resonant devices. This measuring device is integrated on a chip on which the oscillating/resonant device to be measured is also integrated. The circuits and methods described find application in the area of radiofrequency/high frequency electronics RF/HF, in particular adapted to general public applications in mobile communication systems and/or to metrology.

Abstract: Apparatus and methods for wireless data transmission in a multimedia network are disclosed. Disclosed is a network having a source coupled to a sink using a virtual channel that includes a wireless communication channel. A source end of the system provides a packetizing data stream having a stream of payloads such that each payload is associated with its respective originating source stream. The system configured to encode the packetized data stream for wireless transport. A non-wireless source end of the system receives quality of service information from downstream. Thereby enabling adjustments to the source content and packetized data streams.

Abstract: The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

Abstract: A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections.

Abstract: An image sensor formed of an array of pixels, each pixel including a photodiode coupled between a first reference voltage and a first switch, the first switch being operable to connect the photodiode to a first node; a capacitor arranged to store a charge accumulated by the photodiode, the capacitor being coupled between a second reference voltage and a second node; a second switch coupled between the first and second nodes, the second switch being operable to connect the capacitor to the first node; and read circuitry coupled for reading the voltage at the second node.

Abstract: A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode.

Abstract: A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.

Abstract: A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method.

Abstract: The voltage regulators are capable of limiting undershoots of the output voltage without having a similar effect on overshoots because of the presence of a current cancellation network, input with the reference voltage and coupled to the second input of the error amplifier. This current cancellation network is adapted to inject into the second input a unidirectional compensation current of the first and second currents injected by the first and second feedback networks, respectively, the compensation current being determined by time variations of the difference between a replica of the output regulated voltage and the reference voltage and/or by time variations of the reference voltage.