Abstract: An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active.

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: a) arranging the wafer on a surface of an elastic film stretched on a first support frame having dimensions much greater than the wafer dimensions, so that, in top view, a ring-shaped film portion separates this outer contour from the inner contour of the frame; b) performing manufacturing operations by using equipment capable of receiving the first frame; c) arranging, on the ring-shaped film portion, a second frame of outer dimensions smaller than the inner dimensions of the first frame; d) cutting the film between the outer contour of the second frame and the inner contour of the first frame and removing the first frame; and e) performing manufacturing operations by using equipment capable of receiving the second frame.

Abstract: A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance.

Abstract: An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of bit length of 2m bits or less; an addition circuit having 2m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said in columns at a bit position to cause said result to be rounded.

Abstract: A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal.

Abstract: A filtering circuit includes a substrate; an acoustic mirror or a membrane destined to act as a mechanical support of acoustic resonators and to isolate these resonators from the substrate; a first section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer; and a second section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer. The filtering circuit also includes metallic vias implementing an inter stage connection between the lower resonator of a section and the upper resonator of the other section. Preferably, the upper resonators exhibit a piezoelectric layer having a thickness selected in order to achieve an optimal impedance matching between the said first and second sections.

Abstract: The method is for processing a multiplex image, the multiplex including at least one first view intended to be viewed by a first eye of an observer and at least one second view intended to be viewed by a second eye of the observer. The two views are spatially sub-sampled according to complementary grids and mutually spatially shifted. The method includes a demultiplexing of the multiplex image so as to extract the first and the second views. And, for at least one missing pixel of the first view, there is a determination of a first window of the first view containing the location of the missing pixel and representing a first detail in the first view, a determination of a second window of the second view representing the same first detail in the second view, and a formulation of the missing pixel by using the pixels of the second window.

Abstract: An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively.

Abstract: A noise suppression method for a capacitance-to-voltage converter varies a sequence of sensing signal edges during a plurality capacitance measurements to produce a number of noise responses. The sensing signal edges are varied in a repetitive rising and falling edge pattern for each sequence. Three or more such sequences can be used, and the sequence with the highest noise is eliminated and the others are averaged. The noise suppression method can be implemented during calibration and then used for a number of normal acquisitions. The noise suppression method can be applied to capacitance-to-voltage converters having monitoring and integration phases.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.

Abstract: A method for manufacturing a liquid-tight electronic device includes: providing a first printed-circuit board having a first connector; providing a supporting structure having a first opening; forming a first assembly by coupling the supporting structure and the first printed-circuit board in such a way that the first connector extends through the first opening and delimits a bottom gap; and forming a second assembly having a protective shell. The method further includes: depositing a first layer of liquid resin within the bottom gap, and hardening the first layer of liquid resin; depositing a second layer of liquid resin within the second assembly; coupling the first and second assemblies in such a way that the second layer of liquid resin hermetically closes a first interstitial area between the protective shell and the supporting structure; and hardening the second layer of liquid resin.

Abstract: An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal.

Abstract: Controlling a resonant switching system, which includes a first switch and a second switch in a half-bridge configuration for driving a resonant load. A corresponding control system includes command means for switching on and switching off the switches alternatively according to a working frequency of the switching system. The control system includes detection means for detecting a zeroing of a working current being supplied by the switching system to the resonant load in a temporal observation window; the observation window follows each switching off of at least one of the switches, and has a length equal to a fraction of a working period of the switching system. Correction means are then provided for modifying the working frequency in response to each detection of the zeroing in the observation window.

Abstract: A system for the wireless transfer of power includes a first device connected to a power supply source and provided with a first resonant circuit at a first frequency, a second device comprising at least one battery, provided with a second resonant circuit at said first frequency, arranged at a distance smaller than the wavelength associated with said first frequency and not provided with wires for the electrical connection with said first device. The first device is adapted to transfer a first signal representing the power to be sent to the second device for charging said at least one battery and comprises means adapted to modulate the frequency of said first signal for transferring data from the first device to the second device simultaneously with the power transfer. The second device comprises means adapted to demodulate the received signal, corresponding to the first signal sent from the first device, to obtain the transmitted data.

Abstract: A non volatile memory device is provided. The memory device includes a plurality of memory cells and programming means. The programming circuitry is configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. the program means includes a program circuit configured to receive at least one second data word, and, for each second data word, select a corresponding portion of memory cells of the group and send a program current in parallel to discriminated memory cells of the portion based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate said at least one second data word from the first data word.

Abstract: An embodiment of an apparatus includes a receiver operable to receive a message, and a processor operable to determine whether to broadcast the message. For example, the receiver and processor may be disposed on a first vehicle, and the receiver may receive the message from a second vehicle, where the message includes information related to a traffic-related event. The processor may determine whether to broadcast the message to other vehicles based on, e.g., the location of the first vehicle, the location of the second vehicle, the location of the event, or whether the processor has received the message more than once. The processor may determine not to broadcast the message if, based on these or other factors, it determines that the benefit of broadcasting the message is outweighed by the potential of the message, if broadcast, to “clog” a channel over which such traffic-related-event messages are broadcast.

Abstract: A micromechanical structure for a MEMS three-axis capacitive accelerometer is provided with: a substrate; a single inertial mass having a main extension in a plane and arranged suspended above the substrate; and a frame element, elastically coupled to the inertial mass by coupling elastic elements and to anchorages, which are fixed with respect to the substrate by anchorage elastic elements. The coupling elastic elements and the anchorage elastic elements are configured so as to enable a first inertial movement of the inertial mass in response to a first external acceleration acting in a direction lying in the plane and also a second inertial movement of the inertial mass in response to a second external acceleration acting in a direction transverse to the plane.

Abstract: An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition.