Patents Assigned to STMicroelectronics (Alps) SAS
  • Patent number: 11070754
    Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: July 20, 2021
    Assignees: STMicroelectronics Asia Pacific Pte Ltd., STMicroelectronics (Alps) SAS
    Inventors: Hongliang Zhang, Lookah Chua, Celine Mas, Wai Yin Hnin
  • Publication number: 20210192304
    Abstract: A method of managing the power supply of one or more first elements by a second element of a same first device, includes the steps of: sending, to a second device, a time extension request; evaluating during the time extension a power available from an electromagnetic field radiated by the second device; and adjusting the power supply of the second element and of the first element(s) according to the available power.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Julien MERCIER, Pascal NONIER
  • Patent number: 11005490
    Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 11, 2021
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS SA
    Inventors: St├ęphane Le Tual, David Duperray, Jean-Pierre Blanc
  • Publication number: 20210135661
    Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Alps) SAS
    Inventors: Giovanni Luca TORRISI, Domenico aka Massimo PORTO, Christophe ROUSSEL
  • Patent number: 10984845
    Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 20, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Diana Moisuc, Christophe Laurencin
  • Publication number: 20210104457
    Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David AUCHERE, Claire LAPORTE, Deborah COGONI, Laurent SCHWARTZ
  • Patent number: 10971925
    Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Frederic Lebon, Laurent Chevalier
  • Patent number: 10965212
    Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventor: Patrik Arno
  • Patent number: 10944359
    Abstract: A quartz crystal resonator is coupled to an electronic circuit. A capacitive or resistive element is provided for adjusting a frequency of the quartz crystal resonator on activation or deactivation of a function of a circuit. Control is made according to a model of an expected variation of a temperature of the quartz crystal resonator.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Benoit Marchand, Francois Druilhe
  • Patent number: 10944358
    Abstract: A quartz crystal resonator is connected to an array of switchable capacitors or resistors. The switched actuation of elements of the array is controlled by bits of a control word. At least one of the bits of the control word is controlled by pulse width modulation to effectuate a tuning of the oscillation frequency of the quartz crystal resonator.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Benoit Marchand, Francois Druilhe
  • Publication number: 20210067177
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART, Patrick Arnould
  • Patent number: 10924100
    Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 16, 2021
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Alps) SAS
    Inventors: Giovanni Luca Torrisi, Domenico Porto, Christophe Roussel
  • Patent number: 10917106
    Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 9, 2021
    Assignees: STMicroelectronics SA, STMicroelectronics (Alps) SAS
    Inventors: Stephane Le Tual, Jean-Pierre Blanc, David Duperray
  • Patent number: 10917087
    Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 9, 2021
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, Inc., STMICROELECTRONICS (ALPS) SAS
    Inventors: Vanni Poletto, David F. Swanson, Giovanni Luca Torrisi, Laurent Chevalier
  • Patent number: 10886844
    Abstract: A controller for compensating a voltage drop on a cable includes an output stage coupled to a channel configuration pin of the source device, a processor coupled to a power supply pin of a source device, and an error amplifier that includes a positive input coupled to a reference voltage, a negative input coupled to the channel configuration pin, a first output coupled to the output stage, and a second output coupled to the processor. The error amplifier is configured to supply a first signal to the output stage indicating a voltage difference between the reference voltage and a voltage at the channel configuration pin. The output stage is configured to supply an output current to the processor using the voltage drop and a stored current determined using the first signal. The processor is configured to generate a compensated supply voltage on the power supply pin using the output current.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 5, 2021
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventor: Alexandre Pons
  • Patent number: 10879583
    Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 29, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
  • Patent number: 10868522
    Abstract: An optical emission circuit includes a power supply source and a regulation circuit coupled to control the power supply source. An optical source and a first switch are coupled in series to the power supply source. A square pulse signal source has an output coupled to a control input of the first switch. The square pulse signal source is configured to provide a square pulse signal. The regulation circuit regulates the current supplied by the power supply source according to a product of a peak current set point by a duty cycle of the square pulse signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (ALPS) SAS
    Inventor: Xavier Branca
  • Patent number: 10837825
    Abstract: A method of detecting ambient luminous radiation includes resetting and triggering a counter each time a photodiode illuminated by the ambient luminous radiation reaches a discharge threshold. The counter is then being clocked by a clock signal having a first frequency and delivering a counter output signal. The method further includes generating an AC signal representative of the ambient luminous radiation by converting, from digital to analog, a digital signal obtained from the counter output signal.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 17, 2020
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Pascal Mellot, Jean-Jacques Rouger
  • Patent number: 10832780
    Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (GRENOBLE2) SAS
    Inventors: Leonardo Valencia Rissetto, Elise Le Roux, Christophe Forel
  • Publication number: 20200335466
    Abstract: A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 22, 2020
    Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent SCHWARTZ, David KAIRE, Jerome LOPEZ