Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.

Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

Abstract: The present disclosure relates to a method for powering an electronic device. The electronic device includes at least one universal integrated circuit card or at least one secure element; at least one power supply circuit for said card or secure element; and at least one near field communication module. When the near field communication module changes from a standby or inactive state to an active state, the following successive operations are performed: —the components and circuits of said electronic device are started; —programs of the electronic device and said secure card or element are started at the same time.

Abstract: Method for detecting the linear extraction of information in a processor using an instruction register for storing an instruction including an operation code. The method includes monitoring the instructions successively stored in the instruction register including decoding the operation codes, determining the number of consecutive operation codes encoding incremental branches, and generating a detection signal if the number is greater than or equal to a detection threshold.

Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.

Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.

Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.

Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.

Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.

Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.

Abstract: The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.

Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.

Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.

Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.

Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register