Patents Assigned to STMicroelectronics AS
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Patent number: 11971505Abstract: A method includes counting a first set of photons having times of flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having times of flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.Type: GrantFiled: November 30, 2020Date of Patent: April 30, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pascal Mellot
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Patent number: 11973457Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.Type: GrantFiled: May 18, 2021Date of Patent: April 30, 2024Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l., STMicroelectronics Application GMBHInventors: Aldo Occhipinti, Christophe Roussel, Fritz Burkhardt, Ignazio Testoni
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Patent number: 11971313Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: GrantFiled: March 4, 2021Date of Patent: April 30, 2024Assignee: STMicroelectronics SAInventors: Philippe Galy, Renan Lethiecq
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Publication number: 20240136424Abstract: The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm2.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicant: STMicroelectronics (Rousset) SASInventor: Loic BOURGUINE
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Publication number: 20240136351Abstract: The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicant: STMicroelectronics (Rousset) SASInventors: Loic BOURGUINE, Lionel ESTEVE
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Publication number: 20240134056Abstract: A method corrects an ionospheric error affecting pseudo-range measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of the constellation of satellites. The method is performed in a navigation processing procedure performed at a GNSS receiver, receiving pseudo-range measurements previously calculated by the GNSS receiver obtained from a first carrier signal and a second carrier signal in the satellite signals, in particular in GPS bands L1 and L5. The method includes performing a correction procedure of the pseudo-range measurements including applying to the pseudo-range measurements corrections for predictable errors obtaining corrected pseudo-ranges and applying to the corrected pseudo-range measurements a further ionospheric error correction calculation to obtain further ionospheric error correction values.Type: ApplicationFiled: October 4, 2023Publication date: April 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Michele RENNA, Nicola Matteo PALELLA
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Publication number: 20240136260Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.Type: ApplicationFiled: October 23, 2023Publication date: April 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
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Publication number: 20240133843Abstract: An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.Type: ApplicationFiled: October 17, 2023Publication date: April 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Domenico GIUSTI, Marco DEL SARTO, Fabio QUAGLIA, Enri DUQI
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Publication number: 20240134406Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Julien GOULIER, Nicolas GOUX, Marc JOISSON
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Publication number: 20240136433Abstract: The present disclosure concerns an electronic device formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising at least one e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, and an analog circuit for controlling said power transistor.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Loic BOURGUINE, Lionel ESTEVE, Antoine PAVLIN
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Publication number: 20240134973Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.Type: ApplicationFiled: October 15, 2023Publication date: April 25, 2024Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Thomas SARNO
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Publication number: 20240132340Abstract: A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: STMicroelectronics (Malta) Ltd.Inventor: Roseanne DUCA
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Publication number: 20240136350Abstract: The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and a second resistor having a second temperature coefficient different from the first coefficient.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicant: STMicroelectronics (Rousset) SASInventors: Loic BOURGUINE, Lionel ESTEVE
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Patent number: 11968602Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.Type: GrantFiled: June 23, 2021Date of Patent: April 23, 2024Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC.Inventors: Karimuddin Sayed, Chandandeep Singh Pabla, Lorenzo Bracco, Federico Rizzardini
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Patent number: 11967900Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.Type: GrantFiled: July 2, 2021Date of Patent: April 23, 2024Assignee: STMicroelectronics (Rousset) SASInventors: Sebastien Ortet, Olivier Lauzier
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Patent number: 11967544Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.Type: GrantFiled: May 19, 2021Date of Patent: April 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Mauro Mazzola, Matteo De Santa
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Patent number: 11966537Abstract: A method for operating an electronic device, including: determining that a touchscreen is in a low frequency display (LFD) mode, determining whether a self-sensing scan was performed in a previous frame of a plurality of frames; after determining, a self-sensing scan was performed in the previous frame, determining a current duration of time corresponding to a current frame based on a previous duration of time corresponding to the previous frame, the previous frame being a frame immediately preceding the current frame; determining, whether the current duration of time is greater than the previous duration of time; and after determining that the current duration is greater than the previous duration, performing a self-sensing scan after the current duration of time, the current duration of time being measured from a beginning of the current frame, the current duration of time having a duration less than a duration of the current frame.Type: GrantFiled: February 20, 2023Date of Patent: April 23, 2024Assignee: STMicroelectronics Asia Pacific Pte Ltd.Inventors: Sang soo Lee, Chan Hyuck Yun
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Patent number: 11965906Abstract: A closed-loop microelectromechanical accelerometer includes a substrate of semiconductor material, an out-of-plane sensing mass and feedback electrodes. The out-of-plane sensing mass, of semiconductor material, has a first side facing the supporting body and a second side opposite to the first side. The out-of-plane sensing mass is also connected to the supporting body to oscillate around a non-barycentric fulcrum axis parallel to the first side and to the second side and perpendicular to an out-of-plane sensing axis. The feedback electrodes are capacitively coupled to the sensing mass and are configured to apply opposite electrostatic forces to the sensing mass.Type: GrantFiled: July 15, 2022Date of Patent: April 23, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Gabriele Gattere, Jean Marie Darmanin, Francesco Rizzini, Carlo Valzasina
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Patent number: 11965923Abstract: The present disclosure is directed to self-tests for electrostatic charge variation sensors. The self-tests ensure an electrostatic charge variation sensor is functioning properly. The self-tests may be performed while an electrostatic charge variation sensor is active and without interruption to the application employing the electrostatic charge variation sensor.Type: GrantFiled: January 21, 2022Date of Patent: April 23, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Fabio Passaniti, Daniele De Pascalis, Enrico Rosario Alessi
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Patent number: 11965739Abstract: The MEMS gyroscope is formed by a substrate, a first mass and a second mass, wherein the first and the second masses are suspended over the substrate and extend, at rest, in a plane of extension defining a first direction and a second direction transverse to the first direction. The MEMS gyroscope further has a drive structure coupled to the first mass and configured, in use, to cause a movement of the first mass in the first direction, and an elastic coupling structure, which extends between the first mass and the second mass and is configured to couple the movement of the first mass in the first direction with a movement of the second mass in the second direction. The elastic coupling structure has a first portion having a first stiffness and a second portion having a second stiffness greater than the first stiffness.Type: GrantFiled: July 19, 2022Date of Patent: April 23, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Daniele Prati, Luca Giuseppe Falorni, Luca Guerinoni