Patents Assigned to STMicroelectronics Crolles 2 SAS
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Patent number: 11152259Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: GrantFiled: May 22, 2020Date of Patent: October 19, 2021Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
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Patent number: 11145779Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.Type: GrantFiled: March 6, 2019Date of Patent: October 12, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Charles Baudot, Sebastien Cremer, Nathalie Vulliet, Denis Pellissier-Tanon
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Patent number: 11145780Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.Type: GrantFiled: February 12, 2020Date of Patent: October 12, 2021Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Publication number: 20210305311Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.Type: ApplicationFiled: March 12, 2021Publication date: September 30, 2021Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
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Publication number: 20210305306Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.Type: ApplicationFiled: March 24, 2021Publication date: September 30, 2021Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Thierry BERGER, Marc NEYENS, Audrey Vandelle BERTHOUD, Marc GUILLERMET, Philippe BRUN
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Publication number: 20210305309Abstract: The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.Type: ApplicationFiled: March 24, 2021Publication date: September 30, 2021Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Thierry BERGER, Damien JEANJEAN
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Publication number: 20210305502Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.Type: ApplicationFiled: March 29, 2021Publication date: September 30, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Remy BERTHELON, Franck ARNAUD
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Patent number: 11131602Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.Type: GrantFiled: November 13, 2018Date of Patent: September 28, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Patrick Le Maitre, Jean-Francois Carpentier
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Patent number: 11131808Abstract: In one embodiment, a waveguide includes an upstream portion, a downstream portion, and an intermediate portion between the upstream portion and the downstream portion. A first band is disposed on an insulating layer, the first band oriented along a first direction. A first lateral strip and a second lateral strip are disposed on either side of the first band, the first lateral strip and the second lateral strip being thinner or interrupted along the intermediate portion.Type: GrantFiled: August 23, 2019Date of Patent: September 28, 2021Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (CROLLES 2) SASInventors: Charles Baudot, Sylvain Guerber, Patrick Le Maitre
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Patent number: 11131782Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.Type: GrantFiled: November 7, 2019Date of Patent: September 28, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Gilles Gasiot, Fady Abouzeid
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Patent number: 11125946Abstract: A ring resonator electro-optical device includes a first silicon nitride waveguide and a second annular silicon waveguide that comprises a first section running under a second section of the first waveguide. The second waveguide also includes an annular silicon strip having a cross-section increasing in the first section from a minimum cross-section located under the second section.Type: GrantFiled: December 4, 2019Date of Patent: September 21, 2021Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Patrick Le Maitre, Nicolas Michit
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Publication number: 20210288102Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: ApplicationFiled: May 21, 2021Publication date: September 16, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
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Publication number: 20210280721Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.Type: ApplicationFiled: May 18, 2021Publication date: September 9, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Mickael GROS-JEAN, Julien FERRAND
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Publication number: 20210280779Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Simon JEANNOT
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Publication number: 20210272915Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SASInventors: Eric SABOURET, Krysten ROCHEREAU, Olivier HINSINGER, Flore PERSIN-CRELEROT
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Publication number: 20210273082Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.Type: ApplicationFiled: February 15, 2021Publication date: September 2, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Edoardo BREZZA, A;exos GAUTHIER, Fabien DEPRAT, Pascal CHEVALIER
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Publication number: 20210273052Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Julien BORREL
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Patent number: 11107938Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.Type: GrantFiled: February 13, 2020Date of Patent: August 31, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Boris Rodrigues Goncalves, Arnaud Tournier
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Patent number: 11107941Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.Type: GrantFiled: March 5, 2019Date of Patent: August 31, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Charles Baudot, Sebastien Cremer, Nathalie Vulliet, Denis Pellissier-Tanon
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Patent number: 11102429Abstract: In one embodiment, an integrated image sensor includes an array of pixels in which each pixel includes a photosensitive area configured to integrate a luminous signal by generating electron-hole pairs so as to form a first signal representative of the number of electrons in the generated electron-hole pairs and a second signal representative of the number of holes in the generated electron-hole pairs. A first circuit portion is configured to store the first signal sheltered from light. A second circuit portion is configured to store the second signal sheltered from light. A third circuit portion is configured to read the first signal and the second signal and able to perform combination operations between the first signal and the second signal so as to generate a combined signal representative of an image, where the integrated image sensor is tailored to operate in a global shutter control mode.Type: GrantFiled: August 21, 2019Date of Patent: August 24, 2021Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Pierre Malinge, Frédéric Lalanne
