Patents Assigned to STMicroelectronics Crolles 2 SAS
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Patent number: 11269140Abstract: An electro-optic device may include a photonic chip having an optical grating coupler at a surface. The optical grating coupler may include a first semiconductor layer having a first base and first fingers extending outwardly from the first base. The optical grating coupler may include a second semiconductor layer having a second base and second fingers extending outwardly from the second base and being interdigitated with the first fingers to define semiconductor junction areas, with the first and second fingers having a non-uniform width. The electro-optic device may include a circuit coupled to the optical grating coupler and configured to bias the semiconductor junction areas and change one or more optical characteristics of the optical grating coupler.Type: GrantFiled: November 9, 2018Date of Patent: March 8, 2022Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Jean-Robert Manouvrier, Jean-Francois Carpentier, Patrick LeMaitre
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Publication number: 20220059672Abstract: A bipolar transistor includes a stack of an emitter, a base, and a collector. The base is structured to have a comb shape including fingers oriented in a plane orthogonal to a stacking direction of the stack.Type: ApplicationFiled: August 13, 2021Publication date: February 24, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Edoardo BREZZA, Pascal CHEVALIER
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Patent number: 11258148Abstract: An orthomode junction for separating and/or combining orthogonally-polarized radiofrequency wave signals, comprises a body which has a main cavity forming a main waveguide, which has a blind end, and auxiliary cavities forming auxiliary waveguides, which communicate laterally with the main cavity in the vicinity of the blind end thereof, and a deflection insert situated at the blind end of the main cavity and facing the auxiliary cavities, the deflection insert having different shapes on the side of the auxiliary cavities respectively.Type: GrantFiled: June 15, 2020Date of Patent: February 22, 2022Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Victor Fiorese, Frederic Gianesello, Florian Voineau
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Publication number: 20220050010Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: ApplicationFiled: November 1, 2021Publication date: February 17, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Philippe GROSSE, Patrick LE MAITRE, Jean-Francois CARPENTIER
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Publication number: 20220052104Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Stephane HULOT, Andrej SULER, Nicolas VIROLLET
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Patent number: 11251175Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.Type: GrantFiled: September 6, 2019Date of Patent: February 15, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexandre Ayres, Bertrand Borot
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Patent number: 11249133Abstract: A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.Type: GrantFiled: January 17, 2020Date of Patent: February 15, 2022Assignee: STMicroelectronics (Crolles 2) SASInventor: Yann Carminati
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Patent number: 11251084Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: GrantFiled: June 23, 2020Date of Patent: February 15, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
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Publication number: 20220028725Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal GOURAUD, Delia RISTOIU
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Publication number: 20220028726Abstract: A method for forming a capacitive isolation trench in a semiconductor substrate includes digging a trench from a main surface of the substrate, the trench including an upper portion gradually widening from a neck in the direction of a lower portion of the trench. A coating of a first electrically isolating material is formed on the walls of the trench. A first semiconductor material is deposited on the coating, with the deposition being interrupted so as to leave a free space between the walls of the trench, the free space having an opening at the neck. A second electrically isolating material is deposited in the trench, with the deposition resulting in the formation of a plug closing the opening to form a closed cavity. The plug is etched so as to open the cavity, and a second semiconductor material or a metal is deposited so as to fill the cavity.Type: ApplicationFiled: July 15, 2021Publication date: January 27, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Denis MONNIER, Francois LEVERD
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Patent number: 11231548Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.Type: GrantFiled: April 13, 2020Date of Patent: January 25, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Boeuf, Charles Baudot
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Publication number: 20220020816Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
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Publication number: 20220020640Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicant: STMicroelectronics (Crolles 2) SASInventor: Magali GREGOIRE
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Publication number: 20220020924Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.Type: ApplicationFiled: September 28, 2021Publication date: January 20, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Yann CANVEL, Sebastien LAGRASTA, Sebastien BARNOLA, Christelle BOIXADERAS
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Publication number: 20220013654Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis GAUTHIER, Pascal CHEVALIER
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Publication number: 20220013681Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
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Publication number: 20220011479Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.Type: ApplicationFiled: September 22, 2021Publication date: January 13, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Vincent FARYS, Alain INARD, Olivier NOBLANC
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Patent number: 11222957Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.Type: GrantFiled: June 22, 2020Date of Patent: January 11, 2022Assignee: STMicroelectronics (Crolles 2) SASInventor: Magali Gregoire
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Publication number: 20220005850Abstract: An optoelectronic device includes a photodiode. At least a portion of an active area of the photodiode is separated from a neighboring photodiode by a first wall including a conductive core and an insulating sheath and by a second optical insulation wall. The first wall and second optical insulation wall further extend parallel to each other and separate the active area from a memory area of the photodiode.Type: ApplicationFiled: June 30, 2021Publication date: January 6, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Alain INARD, Marios BARLAS
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Patent number: 11212475Abstract: A sensor includes pixels each including: a first transistor and a first switch in series between a first node and an internal node of the pixel, a gate of the first transistor being coupled to a second node; a capacitive element, a first terminal of which is connected to the second node; and a plurality of assemblies each including a capacitance in series with a second switch coupled to the internal node. The sensor includes a circuit configured to control, each time a voltage is stored in one of the assemblies, the interruption of a current between the first node and the internal node: by switching a first potential applied to a second terminal of the capacitive element; or by opening the first switch.Type: GrantFiled: June 2, 2020Date of Patent: December 28, 2021Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (CROLLES 2) SASInventors: Laurent Simony, Pierre Malinge
