Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Manufacturing of cavities
    Patent number: 11171034
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • Filtering device in a waveguide
    Patent number: 11169325
    Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot
  • PIXEL WITH GLOBAL SHUTTER
    Publication number: 20210344866
    Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Pierre MALINGE
  • STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
    Publication number: 20210343788
    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy BERTHELON, Olivier WEBER
  • PIXEL COMPRISING A CHARGE STORAGE ZONE
    Publication number: 20210343766
    Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.
    Type: Application
    Filed: April 8, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris RODRIGUES GONCALVES, Frederic LALANNE
  • Structure comprising a strained semiconductor layer on a heat sink
    Patent number: 11165220
    Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 2, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, Universite Paris-Saclay, Centre National de la Recherche Scientifique
    Inventors: Anas Elbaz, Moustafa El Kurdi, Abdelhanin Aassime, Philippe Boucaud, Frederic Boeuf
  • IMAGE ACQUISITION DEVICE
    Publication number: 20210327936
    Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 21, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael FOUREL, Laurent-Luc CHAPELON
  • INTEGRATED CIRCUIT COMPRISING A SUBSTRATE EQUIPPED WITH A TRAP-RICH REGION, AND FABRICATING PROCESS
    Publication number: 20210327834
    Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • Optical diffuser and its method of manufacture
    Patent number: 11150388
    Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Vincent Farys, Alain Inard, Olivier Noblanc
  • Integrated circuit including bipolar transistors
    Patent number: 11152430
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 19, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
  • Interconnection element and method of manufacturing the same
    Patent number: 11152259
    Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali Gregoire
  • Capacitive optical modulator
    Patent number: 11150533
    Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Frédéric Boeuf, Cyrille Barrera
  • Electronic component manufacturing method
    Patent number: 11152570
    Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Yann Canvel, Sebastien Lagrasta, Sebastien Barnola, Christelle Boixaderas
  • Single photon avalanche gate sensor device
    Patent number: 11145780
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Germanium photodiode
    Patent number: 11145779
    Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles Baudot, Sebastien Cremer, Nathalie Vulliet, Denis Pellissier-Tanon
  • PIXEL OF A LIGHT SENSOR AND METHOD OF MANUFACTURING
    Publication number: 20210305309
    Abstract: The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thierry BERGER, Damien JEANJEAN
  • ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES
    Publication number: 20210305502
    Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 30, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy BERTHELON, Franck ARNAUD
  • CHARGE-COUPLED DEVICE
    Publication number: 20210305311
    Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 30, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • PIXEL OF A LIGHT SENSOR AND METHOD FOR MANUFACTURING SAME
    Publication number: 20210305306
    Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thierry BERGER, Marc NEYENS, Audrey Vandelle BERTHOUD, Marc GUILLERMET, Philippe BRUN
  • Wave guide
    Patent number: 11131808
    Abstract: In one embodiment, a waveguide includes an upstream portion, a downstream portion, and an intermediate portion between the upstream portion and the downstream portion. A first band is disposed on an insulating layer, the first band oriented along a first direction. A first lateral strip and a second lateral strip are disposed on either side of the first band, the first lateral strip and the second lateral strip being thinner or interrupted along the intermediate portion.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 28, 2021
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Sylvain Guerber, Patrick Le Maitre