Abstract: Described herein is a device including mirror control circuitry for controlling a movable mirror. The mirror control circuitry includes drive circuitry for providing a drive signal to the movable mirror, and a processor. The processor cause the drive circuitry to generate the drive signal so as to have pulses with leading edges occurring an offset period of time after a maximum opening angle of the movable mirror and trailing edges occurring an offset period of time before a zero crossing of the movable mirror. The processor may sample a mirror sense signal from the movable mirror at times at which a derivative of capacitance of the movable mirror with respect to time is zero, and then perform an action based upon the samples.

Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.

Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.

Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.

Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.

Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Abstract: An inductor and a shunt switch circuit are connected in parallel between an input node and an intermediate node. A first power transistor is connected between the intermediate node and a ground node. A second power transistor is connected between the intermediate node and an output node. The first and second power transistors are driven in response to a pulse width modulation (PWM) drive cycle having an on-time and an off-time. The input node receives a DC input voltage and a DC output voltage is generated at the output node. A control circuit senses the input and output nodes and determines whether the DC input voltage is within a threshold voltage of the DC output voltage. In response to that determination, the shunt switch circuit is turned on only during the off-time of the PWM drive cycle.

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

Abstract: Disclosed herein is a circuit including a driver circuit applying a received drive signal to a capacitive sensing line of a capacitive touch panel as a boosted drive signal, the driver circuit powered by a boosted supply voltage. A charge pump circuit receives an input supply voltage and output the boosted supply voltage, the charge pump circuit including a voltage sensing circuit to sense the boosted supply voltage and a comparison circuit to compare the sensed boosted supply voltage to a threshold and produce a comparison signal. A control circuit determines a ratio of a pulse width of the comparison signal to the drive signal, and tunes operation of the charge pump circuit to drive the ratio to match a performance threshold.

Abstract: A carrier substrate includes a first network of electrical connections and recess. An electronic chip is mounted to the carrier substrate within the recess. The electronic chip includes an integrated guide of optical waves and a second network of electrical connections. A end section of an elongate optical cable is mounted on one side of the electronic chip with a longitudinal guide of optical waves optically coupled to the integrated guide of optical waves. Electrical connection elements are interposed between a face of the electronic chip and a bottom wall of the recess, such that first connect pads of the first electrical connection network are connected to second connect pads of the second electrical connection network through the electrical connection elements.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.