Abstract: A light sensor includes first and second neighboring photodiodes that are separated from each other by a space. A light-absorbing material is positioned at a location which is vertically above the space between the neighboring photodiodes. A first multilayer interference filter includes a central portion located vertically above the first photodiode and a peripheral portion that at least partly extends to rest on top of and in contact with the light-absorbing material.

Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.

Abstract: A structural body made of semiconductor material includes an active area housing a drain region, a body region and a source region within the body region. An electrical-isolation trench extends in the structural body to surround the active area. A first PN-junction and a second PN-junction are integrated in the structural body between the active area and the trench, respectively located on opposite sides of the active area. The first and the second PN-junctions form a first diode and a second diode, with each diode having a respective cathode electrically coupled to the drain region of the MOSFET device and a respective anode electrically coupled to the source region of the MOSFET device.

Abstract: Disclosed herein is a touch screen controller including a driver circuit applying a drive signal to a drive line of a capacitive touch sensing panel. The driver circuit is powered by an accurate supply voltage. A driver supply circuit receives an input supply voltage and outputs the accurate supply voltage. The driver supply circuit includes a clocked comparator comparing a divided version of the accurate supply voltage to a reference voltage and outputting a comparison signal based thereupon. A voltage control circuit (e.g. a charge pump circuit) generates the accurate supply voltage in response to the comparison signal. The clocked comparator and voltage control circuit are both clocked by a driver supply circuit clock.

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.

Abstract: A contactless communication device is capable of communicating in a contactless way with a reader by using active load modulation. Each frame is preceded by a reception period. An antenna is configured to receive a reader signal during each reception period, and to receive a reader carrier signal and transmit a modulated device carrier signal to the reader during each frame. A processor is configured to carry out, in each reception period, a first synchronization between a signal originating from the reader signal received at the antenna and a device carrier clock signal device generated in the device. The processor is also configured to carry out, within each frame, a modulated device carrier signal suppression process in order to obtain a processed signal, and a second synchronization between the processed signal and the device carrier clock signal.

Abstract: A first resistor and a second resistor are coupled in series between a voltage source and an active load. When the current drawn by the active load exceeds a current threshold corresponding to a maximum admissible voltage drop across the first resistor, a stabilization current is delivered to the node common to the series coupled first and second resistors in such a way as to stabilize the voltage on the terminals of the active load at a threshold value. In the presence of such a current in excess of the current threshold, the current consumed by the active load is measured from the voltage drop across the second resistor. Conversely, if the current is less than the current threshold, the current consumed by the active load is measured from the voltage drop across the first resistor.

Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

Abstract: A DC-DC converter includes a power oscillator connected to a first transformer winding, and a channel conveying a data stream through galvanic isolation by power signal modulation. A rectifier rectifies the power signal to produce a DC voltage. A comparator produces an error signal from the DC voltage and a reference voltage. An analog-to-digital converter converts the error signal to a digital power control value. A multiplexer multiplexes the digital power control value with the data stream to obtain a multiplexed bitstream. A transmitter driven by the multiplexed bitstream performs amplitude modulation of the power signal at a second transformer winding. A receiver connected to the first winding demodulates the amplitude modulated power signal. A demultiplexer demultiplexes the data stream and the digital power control value. A digital-to-analog converter converts the digital power control value to an analog control signal for the power oscillator.

Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.

Abstract: An antenna includes an elongated conductive strip to which at least one capacitive element of adjustable capacitance and at least one inductive element are electrically coupled. The at least one capacitive element is coupled between the strip and ground. The at least one inductive element is switchable in parallel with the at least one capacitive element. The elongated conductive strip is integral with a periphery of a device shell. Adjustment of capacitance and switching of inductance is dependent on device operation.

Abstract: An amplifier circuit generates a control signal as a function of a difference between a reference signal and a feedback signal. The control signal is filtered by a low pass filter circuit to generate a filtered control signal. The control signal is applied to the control terminal of a first ballast transistor which sources current to an output node. The filtered control signal is applied to the control terminal of a second ballast transistor which also sources current to the output node. In response to the sourced currents, an output voltage is generated at the output node. A feedback circuit coupled to the output node generates the feedback signal.

Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.

Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.

Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.

Abstract: A micro-electro-mechanical (MEMS) actuator device includes a frame, and a first functional sub-structure positioned within the frame and mechanically coupled thereto by supporting elements. The first functional sub-structure is subdivided into first and second portions. The first portion is subdivided into first and second sub-portions separated from one another by a first through trench, and the second portion is subdivided into first and second sub-portions separated from one another by a second through trench. First and second piezo-electric structures are respectively carried by the first and second sub-portions of the first portion. Third and fourth piezo-electric structures are respectively carried by the first and second sub-portions of the second portion. A third through trench extends between the frame and the first functional sub-structure except for regions in which the supporting elements are present.

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.