Abstract: An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.

Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.

Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.

Abstract: An oscillator circuit includes a first current generator circuit that generates a current complementary to absolute temperature and a second current generator that generates a current proportional to absolute temperature. A temperature slope control circuit adjusts slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in a complementary fashion and adds the current complementary to absolute temperature to the current proportional to absolute temperature after slope control to produce a temperature independent current. A current control circuit adjusts magnitude of the temperature independent current to produce a magnitude adjusted temperature independent current. A current controlled oscillator generates an output signal as a function of the magnitude adjusted temperature independent current.

Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

Abstract: A method of sensing a temperature includes providing a voltage to reverse bias a PN junction of a junction diode. The PN junction has a junction capacitance. The method includes providing a reverse bias voltage change across the PN junction and detecting a value of the junction capacitance in response to the reverse bias voltage change. The value of the junction capacitance is a function of a temperature of the PN junction. An output signal is generated based on the detected junction capacitance, where the output signal indicates a temperature of an environment containing the junction diode.

Abstract: A resistive microelectronic fluid sensor implemented as an integrated voltage divider circuit can sense the presence of a fluid within a fluid reservoir, identify the fluid, and monitor fluid temperature or volume. Such a sensor has biomedical, industrial, and consumer product applications. After fluid detection, the fluid can be expelled from the reservoir and replenished with a fresh supply of fluid. A depression at the bottom of the sample reservoir allows a residual fluid to remain undetected so as not to skew the measurements. Electrodes can sense variations in the resistivity of the fluid, indicating a change in the fluid chemical composition, volume, or temperature. Such fluctuations that can be electrically sensed by the voltage divider circuit can be used as a thermal actuator to trigger ejection of all or part of the fluid sample.

Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.

Abstract: A multi-phase electric motor includes a stator winding. The multi-phase electric motor is controlled by regulating a current flowing in the multi-phase electric motor in response to an applied voltage. An overload condition of the multi-phase electric motor is detected by monitoring a thermal increase of the value of a stator resistance of the stator winding of the multi-phase electric motor during a steady state condition of said multi-phase electric motor in which the current flowing in the motor has constant phase, and the motor is operating at constant load with constant speed.

Abstract: Mirror control circuitry operates to control a movable mirror. The mirror control circuitry includes drive circuitry for providing a drive signal to the movable mirror, and a processor. The processor causes the drive circuitry to generate the drive signal so as to have pulses with leading edges occurring an offset period of time after a maximum opening angle of the movable mirror and trailing edges occurring an offset period of time before a zero crossing of the movable mirror. The processor may sample a mirror sense signal from the movable mirror at times at which a derivative of capacitance of the movable mirror with respect to time is zero, and then perform an action based upon the samples.

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Abstract: A sensor chip includes registers storing and outputting configuration data, an extraction circuit receiving digital data and extracting features of the digital data in accordance with the configuration data, and a classification circuit applying a decision tree to the extracted features to generate a context of an electronic device into which the sensor chip is incorporated relative to its surroundings, the decision tree operating according to the configuration data. The classification unit outputs the context to the registers for storage. The configuration data includes which features for the extraction circuit to extract from the digital data, and a structure for the decision tree. The structure for the decision tree includes conditions that the decision tree is to apply to the at least one extracted feature, and outcomes to be effectuated based upon whether the extracted features meet or do not meet the conditions.

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

Abstract: A circuit includes a logic circuit and a driver. The driver includes a first NMOS having a gate coupled to the logic circuit and source coupled to a reference voltage, a PAD coupled to a drain of the first NMOS, and a driver protection circuit. The driver protection circuit includes a second NMOS having a drain coupled to the PAD through a capacitor, source coupled to the reference voltage, and gate coupled to a supply voltage, and a resistor coupled between the drain of the second NMOS and the bulk of the first NMOS. The supply voltage transitions low when an electrostatic discharge (ESD) event raises potential at the PAD with respect to either reference voltage or supply voltage such that the second NMOS turns off, resulting in isolation of the bulk of first NMOS from the reference voltage and coupling of the bulk to the PAD using the capacitor.

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

Abstract: Data exchanges between an ultra-wide band communication module and a secure element are controlled such that the data exchanges pass through a near-field communication router. The near-field communication router controls routing of the data exchanges so that the data exchanges do not pass through a host circuit that is also coupled to the near-field communication router.

Abstract: A device includes a touch and pressure sensitive screen having touch pressure sensors and a controller. The controller acquires touch pressure data from the plurality of touch pressure sensors. For each touch pressure sensor, the controller determines whether the touch pressure data from that touch pressure sensor is indicative of abnormal operation of that touch pressure sensor. Where no abnormal operation is indicated, the controller sums the touch pressure data from each of the touch pressure sensors to produce a touch pressure output. Where abnormal operation is indicated, the controller sums the touch pressure data from each of the touch pressure sensors and multiply the sum by a correction factor to produce the touch pressure output.