Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Abstract: A system for detecting objects, for driver assistance equipment in motor vehicles for example, includes a transmitter for transmitting towards an object an optical signal having a signal energy. The optical signal transmitted includes at least one encoded pulse sequence with the signal energy distributed over the pulse sequence. A receiver receives an echo signal resulting from reflection of the optical signal at the object with the time delay of the echo signal is indicative of the distance to the object.

Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.

Abstract: Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.

Abstract: Transient overvoltage suppression is provided by discharging through a Metal Oxide Varistor (MOV) and Silicon Controlled Rectifier (SCR) which are connected in series between power supply lines. The SCR has a gate that receives a trigger signal generated by a triggering circuit coupled to the power supply lines. A trigger voltage of the triggering circuit is set by a Transil™ avalanche diode.

Abstract: A controller chip includes processing circuitry configured to process received samples by estimating trend functions from the samples, subtracting the trend functions from the samples to produce de-trended samples, performing a mathematical transform on the de-trended samples to produce frequency bins. The frequency bins may correspond to unwanted resonance movement of a movable mirror associated with the received samples. The processing circuit further generates an error function from the frequency bins. The error function can be used to generate correction signals for the movable mirror that serve to minimize the error function.

Abstract: A method can be used for analyzing digital images of skin lesions. The images include pixels distributed over a lesion area. Sets of values including a first discrimination value indicative of a weighted average of the image pixels with weighing at the border of the lesion, a second discrimination value indicative of skewness and kurtosis of the distribution of the image pixels, a third discrimination value indicative of the ratio of symmetry and gray-level power of the distribution of the image pixels and calculated. A total additive score of the values in the sets of values is provided and compared with a total score threshold. The first, second and third discrimination values are compared with respective first, second and third discrimination threshold values. An output classification for the image analyzed is provided as a function of the results of the comparing.

Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.

Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.

Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.

Abstract: An electronic device includes a carrier substrate having a front face and an electronic chip mounted on the front face. An encapsulation cover is mounted above the front face and bounds a chamber in which the chip is situated. A front opening is provided in front of an optical component of the chip. An optical element, designed to allow light to pass, is mounted on the cover in a position which covers the front opening of the cover. The optical element includes a central region designed to deviate light and a positioning pattern that is visible through the front opening. An additional mask is mounted on the encapsulation cover in a position which extends in front of the optical element. A local opening of the additional mask is situated in front of the optical component.

Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.

Abstract: Described herein is a video projection system including an optical module with at least one collimated light source to generate a light beam and at least one movable mirror to reflect the light beam. The video projection system also includes a video source producing a digital video stream in accordance with a clock signal and a movement synchronization signal, as well as a projector system. The projector system includes mirror control circuitry configured to control movement of the at least one movable mirror in accordance with the clock signal and the movement synchronization signal, a light source controller configured to control generation of collimated light by the at least one collimated light source, and processing circuitry configured to receive the digital video stream, and to generate control signals for the light source controller based upon the received digital video stream.