Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRMprocessor, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: Device, comprising a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: Device, comprising a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link.

Abstract: A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page.

Abstract: A vehicle navigation system may include an antenna, e.g. a GPS antenna, an output for providing guide advice to the vehicle driver and including a display, a memory encompassing a navigation database with electronic maps stored within, and an electronic controller. The system is capable of detecting the global position of the vehicle on the basis of the electromagnetic waves received by the antenna, associating the global position to the exact road position of the vehicle by comparison with the electronic maps and providing pictorial guide advice to the vehicle driver according to the road position via the display. The system may include a digital camera installed on the vehicle and able to record digital pictures of the outside and to provide the digital pictures to the electronic controller. The pictures are displayed via the display, and pictorial guide advice, e.g. directional arrows, are overprinted to the displayed pictures.

Abstract: An LCD display driver provides adjustable contrast independent of multiplexing requirements by generating each COM signal in a time slot of a repeating signal frame, with each COM signal containing one or more active periods and one or more inactive periods. The relative time proportions of these periods are adjustable. Corresponding SEGMENT signals turn on/off required segments while maintaining an essentially zero DC component. The logic levels and the relative active time and inactive times of the COM and segment signals being adjustable for increasing or decreasing the RMS voltage levels across the LCD element as desired.

Abstract: An LCD display driver provides adjustable contrast independent of multiplexing requirements by generating each COM signal in a time slot of a repeating signal frame, with each COM signal containing one or more active periods and one or more inactive periods. The relative time proportions of these periods are adjustable. Corresponding SEGMENT signals turn on/off required segments while maintaining an essentially zero DC component. The logic levels and the relative active time and inactive times of the COM and segment signals being adjustable for increasing or decreasing the RMS voltage levels across the LCD element as desired.

Abstract: A circuit is provided for controlling a battery-charger device with a closed-loop architecture. The circuit includes sensing means for sensing an operative quantity of the device, control means, and driving means. The control means alternately controls the sensing means to track the operative quantity during a tracking phase and to hold the operative quantity during a holding phase. The driving means provides a regulation signal that regulates the operative quantity based on a comparison between the operative quantity sensed by the sensing means and a reference value. The control means causes the driving means to hold the regulation signal during at least part of each of the holding phases. Also provided is a method of controlling a battery-charger device with a closed-loop architecture.

Abstract: The invention provides a method for removing noise spikes from an electrical input signal having an AC component, comprising the steps of determining the actual rms value of the input signal, low pass filtering the input signal, producing a variable offset, said variable offset being a function of the actual rms value, forming a variable threshold by superimposing the variable offset to the low pass filtered signal, comparing the input signal to the variable threshold, creating a spike detection signal when the input signal passes the variable threshold, and blanking the input signal during the occurrence of the spike detection signal.

Abstract: The invention provides a method for removing noise spikes from an electrical input signal having an AC component, comprising the steps of determining the actual rms value of the input signal, low pass filtering the input signal, producing a variable offset, said variable offset being a function of the actual rms value, forming a variable threshold by superimposing the variable offset to the low pass filtered signal, comparing the input signal to the variable threshold, creating a spike detection signal when the input signal passes the variable threshold, and blanking the input signal during the occurrence of the spike detection signal.

Abstract: A monitoring circuit for a data transmission network having a plurality of transmissive and receptive network nodes and a double-line bus connecting the network nodes and serving for redundant double transmission of digital communications, with a first line (A) and a second line (B) via which communication pulses transferred in the form of time-spaced pulse sequences are transferred in synchronous manner in terms of time slot, a potential change detector is provided by means of which the two lines can each be monitored for the presence of potential change activities and by means of which a condition can be detected in which, during a pulse sequence, potential change activities occur only on the first line, but not on the second line; and a first time measuring circuit is provided by means of which a time measurement of the duration of such a condition can be carried out, and when a predetermined duration of such a condition is exceeded, an error signal is generated.

Abstract: An electric low-pass filter with blocking behavior for a predetermined rejection frequency, comprising a series connection including a FIR filter and an IIR filter, with the parameters of the FIR filter being matched in essence with respect to the blocking behavior at the rejection frequency and the parameters of the IIR filter being matched in essence with respect to the low-pass behavior. It is possible with such a filter to obtain good low-pass behavior with very high attenuation of the frequency to be rejected, with relatively low circuit expenditure and high stability with respect to oscillation tendency.

Abstract: A receiving circuit is described for a CAN (Controlled Area Network) system with digital data transfer via a bus with parallel, redundant pulse signal transfer via two fines. The receiving circuit includes a comparator circuit assembly for differential evaluation of the two pulse signals received via the two lines, with an offset voltage being superimposed on the pulse signal received via one of the two lines prior to said differential evaluation. The comparator circuit assembly superimposes both a positive offset voltage and a negative offset voltage. A bistable multivibrator circuit is connected between the output side of the comparator circuit assembly and the output of the receiving circuit.

Abstract: A method of signal compression of a signal to reduce the large dynamic range, for example, of the output signal of a CD player in such a way that soft passages of a piece of music are reproduced in somewhat louder manner and very loud passages of a piece of music some are reproduced in somewhat less loud manner. The signal compression circuit used therefor can be integrated completely. The audio signal is fed over a volume control, which can be adjusted by the user, and to this end, a digital setting signal in accordance with the adjustment made on the user side, is supplied via a bus line. When the audio signal is strongly increasing, a tracking signal is formed of said signal, with the amplitude thereof being dependent on the medium amplitude of the audio signal. A window comparator compares the tracking signal with a reference value, as a consequence of which the contents of the up/down counter are reduced. This reduced value is added via an adder to the digital setting signal for the volume control.

Abstract: An interface for a data node of a data network including a plurality of data nodes are connected to each other by way of a bus line and activatable in selective manner by address codes transmitted via the bus line. The interface includes an activating address filter allowing addresses intended for the associated data node to be recognized.

Abstract: An electrical resistor integrated in an integrated semiconductor circuit to have a useful resistor with two spaced-apart useful resistor terminal contact regions and a useful resistor region of semiconductor material located therebetween; and an auxiliary resistor having two spaced-apart auxiliary resistor terminal contact regions and an auxiliary resistor region located therebetween.