Abstract: A slope control device for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said slope control device being designed such that it regulates the slope steepness of the potential curve of a first one of both lines to a desired value; compares the slope steepness of the potential curve on one line to the slope steepness of the potential curve on the other line; and compares the slope steepness of the potential curve of the second line as a function of the comparison result.

Abstract: An SC filter with intrinsic anti-alias function for adjustably decreasing or increasing the amplitude of audio signals in a predetermined frequency range. The SC filter includes a filter module having an RC network with at least one frequency-response-determining RC member whose resistor component R is realized in SC technology. The SC filter also includes a setting means connected to the filter module such that its setting determines the frequency response of the SC filter. The setting means also renders possible a neutral setting in which the effective audio signal path of the SC filter circumvents the filter module so that no decrease or increase of the amplitude of individual frequency portions takes place. An anti-alias low pass filter unit is connected into the audio signal path when the setting means is not set to the neutral setting and the anti-alias low pass filter unit is not located in the audio signal path when the setting means is set to the neutral setting.

Abstract: An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value.

Abstract: A method of and a circuit arrangement for data transfer between a master means and slave means, in which bit sequences are transferred each having an address field for addressing the respective slave means to be controlled, a control field for control information, and a data field. The data bit number of the data field may be different depending on the addressed slave means. The bit sequences transmitted from the master means are read back directly to the master means, so that the occurrence of corrupt bits in the bit sequence is recognized and a transfer of the bit sequence recognized as corrupt to the addressed slave means can be prevented.

Abstract: An inductive load is controlled using a PWM control signal at the control terminal of a current switch. In parallel to the first circuit branch containing the inductive load to be controlled, there is located a second circuit branch including a flyback diode and a measuring resistor. The actual current signal corresponding to the current in the inductive load to be regulated, which is formed using the current in the measuring resistor as measurement voltage, is compared to a desired current signal, and the result of the comparison is processed by a PWM circuit to form a PWM control signal for current switch. Due to the fact that measuring resistor is disposed in the circuit parallel to the inductive load to be controlled, a favorable behavior of the power dissipation in the measuring resistor is obtained in accordance with the duty cycle of the PWM control signal. With a preset value of the measuring resistor, the power dissipation and the required chip area can thus be reduced.

Abstract: A comparator having a differential amplifier with a signal input to receive an input signal and a reference input to receive a reference voltage, and having a controllable bias current source for supplying to the differential amplifier a bias current that has a low quiescent current or a higher active current as a function of whether the input signal is constant or variable. The controllable bias current source is further configured to adjust the bias current in accordance with the rate of change of the input signal.

Abstract: A control or adjusting circuit for a load, a desired signal is compared to an actual signal corresponding to the state of the load, and a PWM control signal is generated in a control signal generating circuit in accordance with the comparison result. The control signal opens and closes a current switch coupled to the load. For forming the PWM control signal, the contents of a ramp counter are compared to the contents of an up/down counter by means of a digital comparator. To obtain fast approximation of the two signals to each other in the case of strong deviations between the desired signal and the actual signal, the up/down counter is subjected to relatively rapid counting in case of high control deviations as compared to low control deviations. To this end, the up/down counter is operated with a clock signal of variable frequency that is produced by a voltage-controlled oscillator as a function of the difference between the desired signal and the actual signal.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: An electric circuit configuration for shaping the slew rate of a pulsed output voltage occurring at an output terminal and for detecting a short circuit at the output terminal, having: a switchover control circuit for controlling the slew rate of the output voltage as a function of a voltage curve occurring across an internal resistor in a first switching state, and for feedback-controlling the slew rate as a function of the output voltage curve in a second switching state, and which is in a substantially dead state in a third switching state; a detector circuit which provides a detection signal when the output voltage differs by at least a predetermined value from the output voltage level occurring before edge onset; and a timer circuit for switching the control circuit from the first to the second switching state a predetermined length of time after edge onset if the detection signal is present at this time, and from the first to the third switching state if the detection signal is not present at this time.

Abstract: For an analysis of an electrical behaviour of a specific cell of a monolithically integrated circuit, a simulation model is used which is composed of a fine model part of the cell of interest and a coarse model part of the remainder of the integrated circuit.

Abstract: A DC converter for stepping down DC voltage having two input terminals (E1, E2) to be connected to an input DC voltage source with a high voltage level; two output terminals (A1, A2) for taking a regulated low output DC voltage; a coil (TS) having a center tap (MA) and connected at one end (TA1) with a first one (E1) of the input terminals via an electronic switch device (MOS) and at the other end (TA2) with the second input terminal (E2) via a first capacitor (C1); the charging voltage of the first capacitor (C1) forming the output DC voltage; a second capacitor (C6) connected at one end with a node located between switching device (MOS) and coil (TS) and at the other end with the center tap (MA) via a first diode (D2); a control device (EV, PWM for comparing the charging voltage of the second capacitor (C6) with a reference voltage (REF) and rendering the switch device (MOS) conductive and non-conductive with a pulse-frequency modulated and/or pulse-width modulated switching pulse sequence depending on the

Abstract: A switched capacitor wherein one of the plates of the capacitor to be switched is fed with the input signal via a transistor switch receiving as control signal at the gate thereof a pulse train with predetermined frequency. For compensating the parasitic capacitance of the transistor switch, a compensation component is located between the transistor switch and the capacitor to be switched. This compensation component is formed as an incomplete transistor structure, such as only 1/2 of a transistor, has a drain region in common with transistor switch and has an insulated gate. The parasitic capacitance of the compensation component thus is established mainly by the capacitance between the insulated gate and the drain region and thus corresponds to the parasitic capacitance of the transistor switch, whereby complete compensation with optimized charge transfer is achieved.

Abstract: A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.

Abstract: A device for selection of address words, each having n bit locations and serving for addressing m different receiving locations of a digital communications apparatus, comprising a digital acceptance device via which address words can be selected which are acceptable for the particular receiving location in consideration. The acceptance device includes an address word segmenting device through which each address word received by the receiving location is subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s, a decoder having a decoder input accepting the bit pattern of the address word segment of the particular address word being examined for acceptance, and having a decoder output at which, for each of the possible segment bit patterns, a decoder output bit pattern representing only this segment bit pattern is available.

Abstract: In a fully integrated logarithmic amplifier, an input current is fed via a diode, and in a reference current branch parallel thereto, a constant current flows through a similar diode. A voltage divider forms of the differential voltage between the two diodes a partial voltage on a variable resistor of the voltage divider, which is processed by a differential amplifier for forming the output signal. Parallel to the two current branches mentioned, there is provided an additional current branch having a constant current source and a diode. The differential voltage between the diode of the reference current branch and the diode in the additional current branch is also divided by a voltage divider. A differential amplifier forms of the voltage on the variable resistor of the voltage divider an error signal which changes the variable resistance from which the differential amplifier has formed the error signal as well as the resistance fo the variable resistor of which the output signal is formed.

Abstract: A driver circuit for slope-controlled pulsed switching of a load having a MOS switching transistor switching the load and a control loop with an amplifier having an amplifier input coupled with a switch control pulse source, an amplifier output connected with the gate of the MOS switching transistor, and a feedback capacitor. The driver circuit also includes a switchable current mirror circuit with a current mirror transistor formed by the MOS switching transistor and a diode transistor wired as a current mirror diode, a connection point between the diode transistor and the gate of the MOS switching transistor being connected with the amplifier output. A timer circuit is supplied on the input side with the switch control pulses from the switch control pulse source, and switches the diode transistor into a conductive state for essentially the duration of each switch control pulse edge and otherwise into a nonconductive state.

Abstract: An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storag

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: A device for the selection of address words each having n bit locations and serving for addressing m different receiving locations of a digital communication module, in at least one of the receiving locations, including a digital acceptance module through which address words can be selected. The device has an address word segmenting module through which each address word received by the receiving location can be subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s. The device further has z digital segment filters whose inputs can each be fed with an address word segment, with each segment filter having the function of examining one address word segment each with respect to conformity with a predetermined segment bit pattern, and a filter output signal being available at the output of the respective segment filter, which in accordance with the examination result is either a conformity signal or a non-conformity signal.

Abstract: An electrical switching device including a switch having a control terminal, a control circuit coupled between a first voltage source terminal and a second voltage source terminal and a control signal input coupled to receive a binary switching control signal.