Abstract: Driver and overload protection circuit for an electrical switch means. Switching control pulses with a minimum edge duration are fed to a two stage comparator circuit having first, lower and second, higher comparator threshold values. When the lower comparator threshold value is exceeded by a switching control pulse, the electrical switch means is rendered conducting. There is provided an overload detection circuit which, upon detection of overload of the electrical switch means, effects switching off of the same. For avoiding that turning on spikes upon each turning on of the electrical switch means, for example when switching capacitive loads, lead to deactivation of the switch means, any overload signal of the overload detector means is blocked as long as the instantaneous voltage value of the particular switching control pulse is not above the upper comparator threshold.

Abstract: In a stereo decoder, channel separation takes place with the aid of a demodulator to acquire signals for stereo operation. At low received field strength there is a continuous switchover to mono operation for each channel in the demodulator. For this purpose a switch is located in a signal path between input and output of the demodulator and driven by a PWM signal whose pulse-width repetition rate determines whether solely mono operation, solely stereo operation or a mixture of the two takes place. For generating the PWM signal, the field strength signal is compared with a triangular signal. To permit the switchover points between stereo and mono operation to be aligned by the manufacturer in accordance with the amplitude of the field strength signal, the apparatus contains two limit storage registers in which digital limit signals are set from outside.

Abstract: An electric muting circuit for soft muting of an audio signal is shown. It comprises a digitally controllable attenuation circuit having an audio signal input, an audio signal output and a control signal input and also comprises an up/down counter having a clock pulse input fed with clock pulses to be counted, a counting control input fed with a counting control signal controlling counting start and counting stop, and a count signal output from which a digital count signal is available and which a digital count signal input of the attenuation circuit.