Patents Assigned to STMicroelectronics (Grenoble 2) SAS
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Publication number: 20240146019Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Fabien QUERCIA, Jean-Michel RIVIERE
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Patent number: 11971505Abstract: A method includes counting a first set of photons having times of flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having times of flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.Type: GrantFiled: November 30, 2020Date of Patent: April 30, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pascal Mellot
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Publication number: 20240134406Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.Type: ApplicationFiled: October 11, 2023Publication date: April 25, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Julien GOULIER, Nicolas GOUX, Marc JOISSON
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Publication number: 20240125930Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.Type: ApplicationFiled: October 9, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SASInventors: Robin VASSAL, Jiri ANDRLE, Peter CABAJ, Cyrille TROUILLEAU
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Patent number: 11960033Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.Type: GrantFiled: March 24, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pascal Mellot
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Patent number: 11960718Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.Type: GrantFiled: April 15, 2022Date of Patent: April 16, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.r.l.Inventors: Leonardo Valencia Rissetto, Francesco Tomaiuolo, Diego De Costantini
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Publication number: 20240105129Abstract: An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, each light emitting pixel having at least one subpixel with one or more light emitting diodes positioned on a substrate. The pixel further includes at least one photodetector positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.Inventors: Jonathan STECKEL, Giovanni CONTI, Gaetano L'EPISCOPO, Mario Antonio ALEO, Carmelo OCCHIPINTI
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Patent number: 11935992Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.Type: GrantFiled: October 13, 2022Date of Patent: March 19, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
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Publication number: 20240087977Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.Type: ApplicationFiled: September 11, 2023Publication date: March 14, 2024Applicant: STMicroelectronics (Grenoble 2) SASInventors: Romain COFFY, Jerome LOPEZ
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Patent number: 11929748Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.Type: GrantFiled: November 16, 2022Date of Patent: March 12, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Ugo Mureddu, Gilles Pelissier, Guillaume Reymond
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Publication number: 20240079363Abstract: An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.Type: ApplicationFiled: August 24, 2023Publication date: March 7, 2024Applicant: STMicroelectronics (Grenoble 2) SASInventors: Romain COFFY, Younes BOUTALEB
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Patent number: 11923256Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.Type: GrantFiled: July 16, 2021Date of Patent: March 5, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Olivier Franiatte, Richard Rembert
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Publication number: 20240072214Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
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Patent number: 11916480Abstract: In an embodiment, A switched-mode power supply includes: a first node; a second node configured to receive a DC input voltage; a third node configured to receive a reference voltage; first and second switching transistors; a first circuit configured to control the first switching transistor; and a second circuit configured to control the second switching transistor, wherein the switched-mode power supply is configured to deliver a regulated output voltage at the first node from the DC input voltage, and wherein the first and second circuits are configured to be powered from the output voltage.Type: GrantFiled: October 6, 2021Date of Patent: February 27, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Vincent Pinon
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Patent number: 11916353Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.Type: GrantFiled: April 13, 2021Date of Patent: February 27, 2024Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Fabien Quercia, Jean-Michel Riviere
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Patent number: 11908809Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.Type: GrantFiled: May 20, 2021Date of Patent: February 20, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SASInventors: Eric Sabouret, Krysten Rochereau, Olivier Hinsinger, Flore Persin-Crelerot
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Patent number: 11908514Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configType: GrantFiled: February 8, 2022Date of Patent: February 20, 2024Assignees: STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Antonino Conte, Alin Razafindraibe, Francesco Tomaiuolo, Thibault Mortier
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Patent number: 11908968Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.Type: GrantFiled: June 13, 2022Date of Patent: February 20, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
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Patent number: 11901894Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.Type: GrantFiled: December 20, 2021Date of Patent: February 13, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Elias El Haddad, Tanguy Tromelin, Patrick Bougant, Christophe Matheron
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Publication number: 20240047407Abstract: An integrated circuit package includes at least one electronic chip having a first face fastened onto a first face of a carrier substrate by an adhesive interface. The adhesive interface includes a crown formed of a first adhesive material that is fastened on the periphery of the first face of the electronic chip. The crown defining an internal housing. A second adhesive material, different than the first material, is deposited in the internal housing.Type: ApplicationFiled: August 1, 2023Publication date: February 8, 2024Applicant: STMicroelectronics (Grenoble 2) SASInventors: Younes BOUTALEB, Julien CUZZOCREA, Romain COFFY