Patents Assigned to STMicroelectronics (Grenoble 2) SAS
  • Patent number: 12106724
    Abstract: An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: October 1, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: David Maucotel
  • Patent number: 12096146
    Abstract: The image sensor includes an array of photosensitive pixels comprising at least two sets of at least one pixel, control circuit configured to generate at least two different timing signals and adapted to control an acquisition of an incident optical signal by the pixels of the array, and distribution circuit configured to respectively distribute the at least two different timing signals in the at least two sets of at least one sensor, during the same acquisition of the incident optical signal.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: September 17, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Gregory Roffet, Pascal Mellot
  • Patent number: 12093098
    Abstract: The present disclosure relates to an USB PD-type interface including a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node, and a fifth node; a MOS transistor connected between the fifth node and the second node; a bipolar transistor having a collector connected to a gate of the MOS transistor and an emitter connected to the fourth node or to the fifth node; and a circuit configured to deliver a control potential to a base of the bipolar transistor determined from a current in the first resistor.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: September 17, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Christophe Lorin, Nathalie Ballot
  • Patent number: 12086094
    Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Arnaud Dehamel
  • Patent number: 12081888
    Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: September 3, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Alexandre Mas, Abdessamed Mekki, Cedric Tubert
  • Patent number: 12072724
    Abstract: The present disclosure relates to a device comprising: N low drop-out voltage regulators, N being an integer greater than or equal to 1; a first circuit configured to deliver N set-point voltages to the N regulators which are proportional to the same first current; and a second circuit configured to deliver the first current, wherein the first current is proportional to a reference current modulated based on a sum of the inrush currents of the N regulators.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: August 27, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Alexandre Pons
  • Patent number: 12066881
    Abstract: A method for operating an electronic device includes while a display is in low power mode, detecting based on data collected by a time of flight (ToF) sensor, a movable object within a field of view of the electronic device; in response to the detecting initiating a period of detection having a plurality of frames, the period of detection being a time period over which a distance value indicative of a distance between the movable object and the display is detected; for each of the plurality of frames, changing the distance value to reflect whether the movable object is moving near or further from the electronic device; detecting that the distance value after the period of detection is less than a threshold distance value indicative of the movable object approaching the display; if the distance value is less than the threshold distance value, waking up the display.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: August 20, 2024
    Assignees: STMICROELETRONICS (BEIJING) R&D CO., LTD., STMicroelectronics (Grenoble 2) SAS, STMicroelectronics, Inc.
    Inventors: Arnaud Deleule, Kalyan-Kumar Vadlamudi-Reddy, Darin K Winterton, Jihong Chen, Olivier Lemarchand
  • Patent number: 12066678
    Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: August 20, 2024
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Nicolas Mastromauro, Roy Duffy, Karine Saxod
  • Patent number: 12056912
    Abstract: In an embodiment a method for detecting a presence of at least one object in a field of view of a time of flight sensor includes successively generating, by the time of flight sensor, histograms, each histogram comprising several classes associating a number of photons detected at a given acquisition period, adding several successively generated histograms so as to obtain a summed histogram and analyzing the summed histogram to detect the presence of at least one object in the field of view of the time of flight sensor.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: August 6, 2024
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Shenzhen) R&D Co., Ltd.
    Inventors: Etienne Bossart, Ji Nan Li, Thomas Perotto
  • Patent number: 12057773
    Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: August 6, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: David Chesneau
  • Publication number: 20240258184
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome LOPEZ
  • Patent number: 12051681
    Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: July 30, 2024
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SAS
    Inventors: Deborah Cogoni, David Auchere, Laurent Schwartz, Claire Laporte
  • Patent number: 12048099
    Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Pierino Calascibetta
  • Publication number: 20240231410
    Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
    Type: Application
    Filed: October 12, 2023
    Publication date: July 11, 2024
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Julien GOULIER, Nicolas GOUX, Marc JOISSON
  • Patent number: 12033305
    Abstract: In an embodiment, a method includes: receiving data signals from a plurality of pixels of an array of pixels; generating a plurality of signal-to-noise ratios by determining signal-to-noise ratios for each respective pixel of the plurality of pixels on the basis of the data signals received from the respective pixel; and filtering the data signals received from each pixel of the plurality of pixels by using an adaptive filter configured on the basis of the plurality of the signal-to-noise ratios to generate filtered data signals.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 9, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Cedric Tubert, Jeremie Teyssier, Gregory Roffet, Stephane Drouard
  • Patent number: 12030381
    Abstract: A measurement of the rotation speed of an object is made using a time-of-flight sensor configured to detect a passing of one or more of elements of the object through a given position. The time-of-flight sensor is further mounted on a one-person vehicle configured to protect the one-person vehicle against collisions through the making a time-of-flight measurement of a relative speed between the one-person vehicle and an obstacle.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: July 9, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Thomas Perotto
  • Patent number: 12028639
    Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: July 2, 2024
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Nicolas Moeneclaey, Samuel Foulon
  • Publication number: 20240213972
    Abstract: A differential comparator circuit includes a voltage amplifier of negative gain receiving an analog input signal and generating an inverted analog input signal. The analog input signal and the inverted analog input signal form differential analog input signals. A comparator input circuit includes a first capacitive divider to generate a first signal as an average of the analog input signal and a first ramp signal, and a second capacitive divider to generate a second signal as an average of the inverted analog input signal and a second ramp signal, with the first and second ramp signals being differential ramp signals. The comparator is configured to compare the first and second signals to generate a signal transition having a timing based on the input signal.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 27, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Laurent SIMONY
  • Patent number: 12016670
    Abstract: In accordance with embodiments, methods and systems for utilizing multiple threshold checkers are provided. A range sensor collects measurement data. The range sensor examines the measurement data based on multiple threshold checkers to determine satisfaction of a trigger condition. In response to the satisfaction of the trigger condition, the range sensor provides the measurement data to a host computing device of the range sensor.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 25, 2024
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS, INC.
    Inventors: Kalyan-Kumar Vadlamudi-Reddy, Darin K Winterton, Pierre-Loic Felter, Olivier Lemarchand
  • Publication number: 20240201773
    Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sylvain CHAVAGNAT, Simon VALCIN