Patents Assigned to STMICROELECTRONICS (GRENOVLE 2) SAS
  • Publication number: 20230266357
    Abstract: Micromechanical device comprising: a semiconductor body; a movable structure configured to oscillate relative to the semiconductor body along an oscillation direction; and an elastic assembly with an elastic constant, coupled to the movable structure and to the semiconductor body and configured to deform along the oscillation direction to allow the oscillation of the movable structure as a function of an acceleration applied to the micromechanical device.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 24, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Gabriele GATTERE, Francesco RIZZINI, Nicolo' MANCA
  • Publication number: 20230268421
    Abstract: A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).
    Type: Application
    Filed: February 13, 2023
    Publication date: August 24, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS PTE LTD
    Inventors: Vincenzo ENEA, Voon Cheng NGWAN
  • Publication number: 20230266403
    Abstract: A device includes a driver circuit and diagnostic circuitry coupled to the driver circuit. The diagnostic circuitry includes an on-state diagnostic circuit and an off-state diagnostic circuit. The diagnostic circuitry, in operation: generates a configuration signal associated with an operative condition of the driver circuit based on a comparator output of the off-state diagnostic circuit; diagnoses conditions associated with the driver circuit; and controls operation of the on-state diagnostic circuit based on the configuration signal.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Gaudenzia BAGNATI
  • Publication number: 20230266381
    Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Gaudenzia BAGNATI, Marzia ANNOVAZZI, Diego ALAGNA, Lucia MAGGIO
  • Patent number: 11736148
    Abstract: An embodiment device comprises a phase locked loop and a frequency locked loop having in common the same controlled oscillator. The device is firstly placed in the card emulation mode at the beginning of a communication between the contactless communication device and a contactless reader, the firstly placing comprising synchronizing within the contactless device, an ALM carrier frequency with a reader carrier frequency by operating at least the phase locked loop, and upon reception by the contactless communication device of an indication sent by the reader indicating a further communication in a peer to peer mode with the reader, the device is secondly placed in the peer to peer mode, the secondly placing including deactivating the phase locked loop and operating the frequency locked loop with a reference clock signal and a frequency set point depending on the reader carrier frequency and the frequency of the reference clock signal.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 22, 2023
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS RAZVOJ POLPREVODNIKOV D.O.O.
    Inventors: Marc Houdebine, Kosta Kovacic, Florent Sibille
  • Patent number: 11734221
    Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 22, 2023
    Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.
    Inventors: Rolf Nandlinger, Radek Olexa
  • Patent number: 11736018
    Abstract: An embodiment electronic device includes a first circuit including first and second transistors series-coupled between a node of application of a power supply voltage and a node of application of a reference voltage, the first and second transistors being coupled to each other by a first node, and a second circuit, configured to compare a first voltage on the first node with first and second voltage thresholds.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 22, 2023
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Sebastien Ortet, Didier Davino
  • Patent number: 11734415
    Abstract: An embodiment integrated circuit comprises a first memory zone having a first level of access rights that is configured to store at least one first software application containing encrypted instructions, means for verifying the integrity of the first software application, an encryption/decryption means, for example a first logic circuit, that is configured to decrypt the encrypted instructions which are considered to exhibit integrity, a processing unit that is configured to execute the decrypted instructions, the first logic circuit being further configured to encrypt the data generated by the execution operation and a second means, for example a second logic circuit, that is configured to store the encrypted data in a second memory zone having a second level of access rights that is identical to the first level of access rights.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 22, 2023
    Assignee: STMICROELECTRONICS (GRAND QUEST) SAS
    Inventor: Vincent Berthelot
  • Publication number: 20230261100
    Abstract: A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 17, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando IUCOLANO, Andrea SEVERINO, Giuseppe GRECO, Fabrizio ROCCAFORTE
  • Publication number: 20230258709
    Abstract: An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Carlo CAIMI, Massimiliano PESATURO, Stefano Antonio MASTROROSA, Alfredo Lorenzo POLI, Marco DELLA SETA
  • Patent number: 11726543
    Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 15, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar
  • Patent number: 11728404
    Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 15, 2023
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Paolo Badalá
  • Patent number: 11725990
    Abstract: A thermographic sensor is proposed. The thermographic sensor includes a plurality of sensing elements each comprising at least one thermo-couple. The thermographic sensor is integrated on a semiconductor on insulator body that is patterned to define a grid suspended from a substrate; for each sensing element, the grid has a frame with the cold joint of the thermo-couple, a plate with the hot joint of the thermo-couple and one or more arms sustaining the plate from the frame. The frames include one or more conductive layers of thermally conductive material for thermally equalizing the cold joints with the substrate. Moreover, each sensing element may also include a processing circuit for the thermo-couple that is integrated on the corresponding frame. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 15, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Maria Eloisa Castagna, Giuseppe Bruno
  • Publication number: 20230251078
    Abstract: A method is provided for controlling an electronic apparatus on the basis of a value of a lid angle between a first hardware element accommodating a first magnetometer and a second hardware element accommodating a second magnetometer. The method includes acquiring, through the magnetometers, first signals representing an orientation of the hardware elements. A calibration parameter indicative of a condition of calibration of the magnetometers is generated on the basis of the first signals. A reliability value indicative of a condition of reliability of the first signals is generated on the basis of the first signals. A first intermediate value of the lid angle is calculated on the basis of the first signals. A current value of the lid angle is calculated on the basis of the calibration parameter, of the reliability value, and of the first intermediate value, and the electronic apparatus is controlled on the basis of the current value.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Federico RIZZARDINI, Stefano Paolo RIVOLTA, Lorenzo BRACCO, Marco BIANCO
  • Publication number: 20230253895
    Abstract: MEMS actuator including: a substrate; a first and a second semiconductive layer; a frame including transverse regions formed by the second semiconductive layer, elongated parallel to a first direction and offset along a second direction, the frame being movable parallel to the second direction.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 10, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Andrea OPRENI, Valentina ZEGA, Attilio FRANGI, Gabriele GATTERE, Manuel RIANI
  • Publication number: 20230251795
    Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Fabio Enrico Carlo DISEGNI, Federico GOLLER, Dario FALANGA, Michele FEBBRARINO, Massimo MONTANARO
  • Patent number: 11721657
    Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 8, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 11721202
    Abstract: A remote access device and methods of operation thereof are provided for accessing a physical object or location. The remote access device includes an accelerometer, a wireless transmitter, and control circuitry. The control circuitry causes the wireless transmitter to transition between a first operating mode and a second operating mode in response to receiving signals from the accelerometer indicating a first change in motion states of the remote access device. The control circuitry causes the wireless transmitter to transition between a first operating mode and a second operating mode in response to receiving signals from the accelerometer indicating a second change in motion states of the remote access device. The control circuitry further causes the wireless transmitter to transition between the first operating mode and the second operating mode in response to receiving signals from the accelerometer indicating a third change in motion states of the remote access device.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: August 8, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Stefano Paolo Rivolta, Federico Rizzardini, Daniele Arceri, Alessandra Maria Rizzo Piazza Roncoroni, Marco Bianco
  • Patent number: 11720205
    Abstract: A method for reporting touch on a touchscreen includes detecting first touch data from the touchscreen corresponding to a first touch on the touchscreen; determining coordinates of the first touch from the first touch data; reporting the coordinates of the first touch at a first time; determining predicted coordinates of a second touch based on a linear regression of historical touch data; and reporting the predicted coordinates of the second touch at a second time, where the second time occurs after the first time.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: August 8, 2023
    Assignees: STMICROELECTRONICS LTD., STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventors: Yuan Yun Wang, Pengcheng Wen, Yingying Sun, Yue Ding
  • Patent number: 11717825
    Abstract: The valve is formed in a valve body housing a first path portion, a second path portion, and an coupling zone between the first and second path portions. A shutter is arranged in the coupling zone and has a shutting portion of ferromagnetic material that is deformable under the action of an external magnetic field between an undeformed position, wherein the shutter closes the coupling zone, and a deformed position, wherein the shutter at least partially frees the coupling zone. The shutting portion of the shutter is formed by a rubber membrane incorporating particles, for example of ferrite particles.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 8, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Davide Cucchi, Lorenzo Bruno, Francesco Ferrara