Abstract: In a method for providing a program guide in a program receiver, program schedule data is received, wherein the program schedule data associates programs with time slots on a particular channel of a plurality of channels. For a first time slot of a virtual channel, and using the program schedule data, a first program is selected from a first channel available for reception in a first selected time slot. For a second time slot of the virtual channel, a second program is selected from a second channel available for reception in a second selected time slot. In response to a request to display a schedule of programs, a schedule of the virtual channel is displayed, including the first and second programs scheduled respectively in the first and second time slots of the virtual channel.

Abstract: A subframe structure for a wireless community uses a master common subframe and second master common subframe method to give BSs different priorities to serve overlapping areas in common subframes. The subframe structure and corresponding method can increase overlapping cells' capacity and reduce interference.

Abstract: A thyristor power control circuit reduces EMI and maintains a holding current in the thyristor to prevent flickering at a load. The power control circuit includes a thyristor configured to receive an input AC voltage, and responsive to a gate pulse generates a modified AC voltage. A rectifier receives the modified AC voltage and generates a rectified DC voltage. A power converter coupled to the rectifier receives the rectified DC voltage and generates a controlled output current. A damping circuit coupled to an output terminal of the rectifier includes a damping resistor for maintaining the holding current in the thyristor during an ON period of the thyristor. The damping circuit includes a first capacitor coupled in series to the damping resistor and a diode coupled in parallel to the damping resistor. The diode enables the first capacitor to discharge without causing power loss at the damping resistor.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: Methods and systems are described for enabling the operation of a stereoscopic viewing device such that the viewing device provides a movable viewing window that enables the 3D rendering of 3D image data displayed by a backlit LCD device. In a particular implementation, the systems and methods disclosed herein are operable to control the operation of a pair of LCD shutter glasses.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption.

Abstract: Clean and reliable channel sensing during dynamic frequency hopping over a plurality of overlapping wireless regional area network (WRAN) cells is conducted using a minimum number of channels. By coordinating a phase-shift of the operation periods of each WRAN cell over a minimum number of working channels, interruption-free communication and data transmission for each of the WRAN cells as well as interference-free channel sensing can be achieved.

Abstract: A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region.

Abstract: A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.

Abstract: Methods and systems for transmitting video pixel data from a transmitter component, such as a controller, to a receiver within a monitor are described. Video data is received at a transmitter at an incoming pixel rate based on a pixel clock. The data is transmitted to the receiver at a link symbol clock rate and is drained from the receiver at the pixel clock rate, which is regenerated by the receiver using the link symbol clock frequency, an M video value, and an N video value. The M video value (Mvid) is determined by the transmitter based on the incoming pixel rate and the N video value (Nvid) may be constant. An accumulator is used within the transmitter to ensure that the transmitter and receiver create a balanced system.

Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.

Abstract: Collisions between tunneled direct link setup (“TDLS”) requests are resolved by associating each request with a priority value. Upon issuing a TDLS request the encapsulated frame is associated with a priority value. When a station, which is waiting for a response from a recently issued TDLS request, receives a TDLS request from another station, a collision occurs. The collision is resolved by comparing the priority value associated with the TDLS request initiated by the station and the TDLS request received. The TDLS request with the higher priority value is pursued while the TDLS request with the lower priority value is ignored. The priority value can be based on the sending station's MAC address or other value which can differentiate the TDLS requests.

Abstract: A system and method for improving performance while transferring encrypted data in an input/output (I/O) operation are provided. The method includes receiving a block of data. The method also includes dividing the block of data into a plurality of sub-blocks of data. The method further includes performing a first operation on a first sub-block. The method also includes performing a second operation on a second sub-block at substantially the same time as performing the first operation on the first sub-block. The method still further includes reassembling the plurality of sub-blocks into the block of data.

Abstract: Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.