Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract: A computer system, including a central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, a set of latches, each latch having an input and an output, and circuitry that couples at least one latch in the set of latches to at least two watchpoints in the set of watchpoints so that there is a predetermined relationship between triggering of the at least two watchpoints. A method of filtering debugging data in a computer system is also provided.

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein said relocation instructions includes a data retrieval instruction having a symbol field identifying a symbol and an attribute field identifying a symbol attribute associated with said identified symbol to be retrieved, the method includes: reading at least one relocation from said set of relocations instruction and where said relocation instruction is a data retrieval instruction, determining the symbol identified by the symbol field and retrieving one of said plurality of symbol attributes associated with said symbol in dependence on the contents of the symbol attributes field of said instruction.

Abstract: Apparatus for re-assembling information cells of messages, comprising a message memory, a message data memory, a location memory, and loading apparatus. The message memory stores each message in blocks that can be different lengths. The message data memory stores, for each message, message data defining a location in message memory, a position in the block, and a length of the block that is to receive the cells of the message. The location memory stores, for each message, an indication of the location of the message data. The loading apparatus receives the cells, and for each cell, accesses location memory to determine the location of message data, stores the cell in the message memory at the indicated location, increments the message data defining the location and the position, and compares the incremented position with the stored length of the block to determine whether the end of the block has been reached.

Abstract: A level shifter uses a current mirror as a current switch connected to the drains of two oppositely-driven FETs. A switch selectively connects the current mirror to its power supply so that no quiescent DC current flows.

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract: An integrated current reference comprises two current mirrors, the gate source voltage of one of the current mirrors being offset by a voltage reference element, which in an embodiment consists of an on MOSFET.

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table.

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

Abstract: The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

Abstract: A voltage converter comprises an input, an output and a current control arrangement for controlling the output current of the voltage converter circuit. The current control arrangement comprises a first mode, when the voltage output by the converter circuit is above a threshold voltage, and a second mode in which the voltage output by the circuit is below the threshold voltage. The first and second modes are controlled by the same current control arrangement. The current control arrangement comprises comparing means arranged to receive a reference voltage wherein the reference voltage is a voltage offset associated with at least one of the inputs of the comparing means.

Abstract: A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract: A computer system includes on-chip a CPU with an addressable module and a memory interface, the module having packet generating circuitry for event request or control packets, the CPU being operable to generate event request packets, memory access packets or control packets having a common format with packets generated by said module.

Abstract: Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0′, s1′, . . . ) and corresponding to the addition of the third binary number and one.

Abstract: A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instruction is subjected by the system and a set of locations for members representing the instruction. A model execution program is then executed on the computer which calls the class definition for each instruction, invokes one of the functional methods and loads the locations of the entry with state information depending on the functional method to create a functional component. The functional component is loaded into memory and the state information of the functional component modified independence on a subsequently invoked functional method by the model execution program.

Abstract: A circuit for generating an output voltage proportional to temperature with a required gradient, the circuit including a first stage arranged to generate a first voltage which is proportional to temperature with a predetermined gradient, the first stage including first and second bipolar transistors with different emitter areas having their emitters connected together and their bases connected across a bridge resistive element, wherein the collectors of the transistors are connected to an internal supply line via respective matched resistive elements as the voltage across the bridge resistive element is proportional to temperature; a differential amplifier having its input connected respectively to the collectors, and its output connected to stabilisation circuitry connected between first and second power supply rails and an internal supply line which cooperates with the differential amplifier to maintain a stable voltage on the internal supply line despite variations between the first and second power supply