Abstract: An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which identifies for each of a plurality of pixels on the shadow receiving surface a grey level representing the intensity of shadow in each pixel. The intensity is determined utilizing the distance between the shadow-casting object and the shadow-receiving object.

Abstract: An application program runs on an embedded processor connected via a link to a host. When the application program identifies a need for communication over said link, it reads a pointer location to see whether its contents represent a valid address in memory, and if so the program calls that address. It then checks the code at the address to see whether an entry point is stored there, and if so uses that entry point to access a subroutine enabling communication over the link.

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values that are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract: A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system.

Abstract: An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers. Each memory cell of the RAMs is connected via a respective bit line to one of the plural sense amplifiers. The sense amplifiers of the tag RAM have respective outputs coupled to a first input of the comparator. The comparator having a second input for address information and an output for selectively enabling data output from sense amplifiers of the data RAM. The memory cells of the tag RAM are arranged to have a higher current drive than the memory cells of the data RAM.

Abstract: A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the

Abstract: A linker and a method of linking object code modules using the linker is described in which a mechanism is defined for defining and passing relocations, termed compound relocations, in the object files, the compound relocations being expandable by the linker into a sequence of relocations all at the same offset. Each compound relocation has a type field denoting a compound relocation type indicator and an offset field indicating the offset where the compound relocation is to be expanded. The method comprises reading a compound relocation, recalling a predefined sequence of relocations, and executing the predefined sequence at the same location as the compound relocation. By defining compound relocations for frequently performed calculations object file bloat can be avoided, as the same sequences are not repeatedly written in the object code files.

Abstract: To enable a processor connected to a host computer to run programs that are dynamically loaded by the host, a stack is loaded into its memory, and the location of the stack, or information enabling that location to be found are stored in a memory location reserved as a vector. The programs are then dynamically loaded into said memory; and a set location in the stack is used to store the entry point into the dynamically loaded file.

Abstract: A method is described for converting a data set for use with a digital model of a hardware cell into an expanded data set for use with an analog model of the hardware cell. The method including the steps of determining the signal required to drive one or more pins of said analog model by analyzing whether the signals used in said digital model are in a first category or a second category, said first category containing relatively simple signals and said second category containing relatively complex signals, and providing the signal required for the one or more pins in the analog model in dependence on said analysis.

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract: A computer system is formed by two interconnected chips each having on chip a CPU connected to a module by an on chip and data path, for distributing event request packets, the paths of the two chips being connected through external ports so that addresses on each of the paths form part of a common address space addressable from either chip.