Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-strin

Abstract: A register of a processor is set to one value when a host is connected to the processor and to a second value when no host is connected. The processor then starts execution after reading the register contents, and if it finds that the second value is stored it writes a set value to a pointer storage location. When the one value is stored, it leaves the content of the pointer location unaffected.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract: A cache memory and method for operating a cache memory are provided which comprise a tag RAM, tag RAM sense amplifier circuitry, data RAM sense amplifier circuitry and decision circuitry. Timing difficulties exist in determining whether or not a hit has occurred and in outputting the data from the data RAM upon occurrence of a hit. Upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and is compared with input address information. A decision is reached as to whether or not identity exists. Only when the result of that decision has been validly determined can data be output.

Abstract: An executable program is prepared from a plurality of object code modules, at least one of the object code modules including section data specifying a plurality of code sequences each associated with relocation instructions identifying condition parameters. Only one of the code sequences is selected for inclusion in the executable program, determined by whether the condition for that parameter is satisfied. A linker for preparing the executable program includes a stack, a relocation module for reading the relocations, carrying out the relocation operations and selecting code sequences for inclusion in the executable program in dependence on values taken from the stack, a section data module for holding section data which is subject to the relocation operations, and a program forming module for preparing executable programs. Also disclosed is a method of assembling an object code module such that the assembled object code module includes the conditional code sequences.

Abstract: There is disclosed a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU and a communication bus providing a parallel communication path between the CPU and at least one of the module with logic circuitry. The integrated circuit device further comprises an external communication port connected to the bus, having an internal parallel format for connection to the bus. The external port further has an external signal having an external format less parallel than the internal format. Translation circuitry is provided to effect conversion between said internal and external formats. There is also disclosed a method of operating such a computer system.

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract: A modelling tool for use in defining an ASP which receives as its input an input file which for each of a set of peripherals defines the functional attributes of that peripheral in a high level language with an input data structure and which generates from the input file, (i) an interface functions file, which defines the communication attributes of the peripheral with the processor and the functional attributes of the peripheral in a manner independent of any particular data structure, (ii) a test functions file which defines the communication attributes of the processor with the peripheral in a manner independent of any particular data structure, and (iii) a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table.

Abstract: A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract: Integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply. The secondary circuit includes a control signal output for supplying a control signal to the clock circuit and a clock data output for outputting new clock data to the clock circuit.

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including special relocations that have a type field for identifying the nature of a function to be implemented by the special relocation. The function is selected from a plurality of arithmetic and logical functions. A method of preparing the executed program includes reading the special relocations, determining from the type field the nature of the function to be implemented, carrying out the selected arithmetic or logical function to generate a result value and using the result value in a subsequent special relocation operation. The method may be executed by a linker having a relocation module for reading the special locations and carrying out the relocation operations.

Abstract: An executable program is prepared from a plurality of object code modules, each module including relocation instructions having an instruction format which includes a classification field for holding a relocation class indicator and a set of relocation fields for holding relocation data. The meaning of the relocation data depends on the class indicator. The instruction format is common to first and second classes of relocations. The executable program is prepared by reading the relocation instructions and determining from the relocation class indicator the class of the relocation instruction and executing the relocation operations on section data in dependence on the class of relocation instruction indicated by the relocation class indicator.

Abstract: There is disclosed a circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data, so as to retain only those parts of the digital data stream required by the receiver. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver.

Abstract: A current source circuit is described for generating control current. The circuit is capable of generating a very accurate reference current and in particular dealing with the problem which can arise from injected noise. A feedback loop is implemented to reject the charge injection noise.

Abstract: An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received.

Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device via an adapter device; the integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, the integrated circuit further comprising an external communication port connected to the said bus on the integrated circuit chip, the port having an internal connection to the said bus of an internal parallel signal format and an external connection to the adapter unit of a first external format less parallel than the said internal format; the adapter device being connected to the external communication port with the first external format and to the external computer with a second external format having a higher latency than the first external format, the adapter device having an interface for translating between the first external format and the second external format; t