Abstract: A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas, and a buffer; a first storage information memory for holding first storage information a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Abstract: A computer system comprises on-chip a CPU with at least one different module, both having circuitry to generate two types of address request packets, one being a control command packet to which a destination device must respond on receipt and the other type being an interrupt request with a priority indicator for a selective response by the destination device.

Abstract: A data stream processing device for processing a succession of information datagrams from multiple data streams, each datagram comprising a payload and an identifier identifying the data stream of which the datagram forms part, the device comprising: a storer for storing an indication of which of the data streams are required for use; a memory; and a datagram processor connected to the storer and the memory and arranged for: receiving incoming datagrams, reading the identifiers of received datagrams and thereby identifying the data stream of which each datagram forms part, and storing in the memory received datagrams that form part of a data stream required for use, and if successively received datagrams that form part of a data stream required for use are interspersed by one or more received datagrams that do not form part of a data stream required for use, storing an indication of the spacing between the said successively received datagrams.

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively “deleting” the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an “even” mark space ratio.

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract: A circuit is described which allows a scan latch to selectively pass inputs derived from either of two test outputs, e.g. scan test and built-in self-test data, but which does not apply an added delay to a data path when this is instead selected.

Abstract: Data stream transfer apparatus for receiving a data stream of data cells at variable time intervals and transmitting data frames at predetermined time intervals, including a receiving apparatus, a buffer memory, a data transfer interface, a central processing unit (CPU), and a memory access unit. The receiving apparatus receives the data cells and stores them in the buffer memory. The data transfer interface transfers data frames out of the apparatus at the predetermined time intervals and generates an indication that the data frame has been transferred. The memory access unit receives data defining a location of a data frame in the buffer memory, accesses the buffer memory to retrieve that data frame and transmits that data frame to the data transfer interface. The CPU, upon receiving the indication, determines a time for transfer of a subsequent data frame, and upon reaching that time, transmits to the memory access unit the location of the subsequent frame in the buffer memory.

Abstract: A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Abstract: An arbiter for arbitrating between a plurality of requests from a plurality of requesters, said arbiter being arranged to assign an order of priority of said requesters, the requester having the highest priority and which has made a request winning the arbitration, wherein the arbiter determines a new priority for said winning requester, said winner being given a priority different from the lowest priority.

Abstract: A method of automated generation of a set of design data defining a system model from an architecture database which is configured to hold in an electronic storage medium architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key, the method comprising, reading the primary key for each architectural parameter, generating in an electronic storage medium a structured definition entry of the architectural parameter in an electronically readable format, the structured definition entry being associated with an identification field defining the parameter, and loading the primary key into the identification field and the subsidiary data into the structured definition file, and wherein the structured definition entry takes the form of a programming definition of the architectural parameter in a modelling language.

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching device, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching device, activatable by the common word line, for cou

Abstract: A data reception unit for receiving a plurality of data streams over a data chanel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation-based on the identity portion.

Abstract: A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values, and storing each data string in a register of the computer store in which its sub-strings are not individually addressable; and performing a series of data reordering steps operating on one or more of said data strings to reorder said data values; the reordering operation being a scan-wise reordering operation.

Abstract: A test circuit for memory having plural memory cells and address latches responsive to addressing circuitry for reading/writing to said memory cells in a normal mode, has first connecting circuitry for connecting the address latches to form a linear feedback shift register. The linear feedback shift register is responsive to a clock signal to provide a sequence of addresses for testing the memory in a test mode.

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2m+1 and for bit lengths n not of a binary order, the number (m+2) of logical stages is nbo=2m+1, where nbo is the next largest binary order after n.

Abstract: A memory map evaluation tool is provided which allows a program to be organised in a manner most compatible with use of a cache. This is done by executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract: An apparatus and method for determining a minimum clock delay provided to sense amplifiers of a memory array. The method first determines a response time of the overall memory circuit by varying the delay of an external clock until the output of the memory circuit is just valid. Then an externally provided sense amplifier clock is substituted for the internal sense amplifier clock and the instant of application of the externally provided sense amplifier clock is varied until the circuit output is just valid.