Abstract: Circuitry for processing data includes a plurality of filters arranged in parallel. Input data is stored. The input data is applied to the plurality of filters to provide at least two parallel results. An operation is carried out with respect to the results.

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract: The image sensor includes an array of pixels. Each pixel has a pinned photodiode which transfers charge via a transfer gate to a floating diffusion, from which output is provided by a source follower. Each column has a voltage supply line and a signal line. Each row has a transfer gate control line, a read/reset control line, and a read/reset voltage line which receives alternately zero volts and a predetermined positive voltage from a decoder circuit.

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract: Data reception apparatus for receiving and processing a data stream including a stream of data units, the data apparatus comprising: a buffer; a data reception controller for receiving data units from the data stream, storing received data units in the buffer, and if the amount of data from the data stream that is stored in the buffer exceeds a predetermined amount, generating a buffer load interrupt for the data stream; and a processor responsive to the buffer load interrupt to: a) disable handling of further buffer load interrupts for the data stream; and b) repeatedly activate a routine to process a single data unit from the data stream that is stored in the buffer until all the data units in the buffer have been processed and then reset the buffer.

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table.

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract: A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. The first series of data pathways passes through a cryptographic circuit causing data to be encrypted or decrypted, and the other series of data pathways provides an unhindered route. When a data access request is made by a device, the data is selectively routed along one of the two series of data pathways according to the identification of the device making the data access request. In one example, if data is transmitted from a device to the external memory, the data is selectively encrypted before being stored in the external memory if the device transmitting the data is identified as secure.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract: A system for providing an assembler for a microprocessor has a file which contains data describing the instruction set of the microprocessor. A translation device for translating into machine language accesses the instruction set descriptors to constrain the machine code output of the assembler to conform to the architecture of the instruction set.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: An integrated circuit restricts use of a data item and includes a data memory storing the data item; a value memory storing a value; a signature input that receives a signature derived from data in a data item field and a value in a value field, the signature being in a coded form; a decoding circuit that decodes the signature and outputs information representing the data in the data item field and the value in the value field; and a comparison circuit that receives the decoding circuit output, determines whether the information representing the data from the data item field corresponds to the stored data item and whether the information representing the value from the value field corresponds to the value stored in the value memory, and outputs a comparison signal according to the determinations. The circuit restricts the use of the data item according to the comparison signal.

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract: A pinned-photodiode image sensor using shared output amplifiers, for example output amplifiers in the 2.5T arrangement has transfer gate control lines alternating or cross-coupled between successive columns or adjacent rows. This assists in removing row-row mismatches. In preferred embodiments, the approach is applied to Bayer pattern RGB sensors, and allows the gain and/or the exposure of green pixels to be controlled separately from those of red and blue pixels.

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor. An additional instruction monitor checks the code instructions from the CPU and also impairs the operation of the circuit unless the address of code requested is in a given range. The code is in the form of a linked list and the range is derived as a linked list table during a first check.