Abstract: A method of forming an executable program from a plurality of object code modules where each object code module includes a plurality of relocation instructions having at least one information output relocation with a field indicating information to be output. The method includes reading a relocation instruction from one of the object code modules and, when the read relocation instruction is an information output relocation, displaying the information indicated in the field in a human readable form.

Abstract: A data processor formed on a single integrated circuit and capable of connection to an external memory, the data processor including: a central processing unit; a local memory including a debug memory area; a plurality of interrupt inputs; an interrupt handler coupled to the interrupt inputs for interrupting the central processing unit in response to interrupt signals received on the interrupt inputs, and being arranged to periodically store in the debug memory area of the local memory data indicative of the status of the interrupt handler; the data processor being adapted to, after having been reset, perform a start-up routine including the step of outputting the contents of the debug memory area to the external memory.

Abstract: A semiconductor integrated circuit comprises a plurality of combinational logic components, a memory and a testing arrangement for configuring the memory prior to testing the combinational logic components using one or more scan chains. The arrangement includes a bit pattern generator for generating a predetermined bit pattern for writing to the memory, a switching arrangement for selectively switching the memory input to receive data from the combinational logic components or from the data generator. The switching arrangement and data generator are arranged to input the predetermined bit pattern to the memory prior to testing the integrated circuit.

Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.

Abstract: The data communication system includes a first control device, a second data device and a data link, including a first transmission link and a second transmission link, between the second data device and the first control device. A data driver enables data transmission from the second data device to the first control device across the data link, and a differential controller is adapted to generate a voltage differential between the first transmission link and the second transmission link. A detector detects differences in voltage levels between the first transmission link and the second transmission link. The data communication system enables bi-directional communication between integrated circuit devices over a serial communication link avoiding the necessity for clock, chip enable and control connections on the data device and is particularly useful for communication between an image sensor and coprocessor.

Abstract: A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.

Abstract: A linker is described and the method of forming an executable program from object code modules using the linker. The linker uses a linker control language in the form of an ordered sequence of relaxation instructions. The relaxation instructions include a jump relaxation instruction which specifies the instruction count of the relaxation instruction which is subsequently read. In this way, more flexibility can be provided for linkers.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A decoding apparatus for decoding digital video data, in a data memory including registers, each register being capable of storing a data strings with a plurality of data sub-strings such that the data sub-strings are not individually addressable; an input for receiving compressed video information represented by a matrix of data values and loading each data value in order into a respective one of the sub-strings; and performing an inverse zigzag operation on the matrix of data values by executing a series of reordering operations on the data strings to reorder the data sub-strings comprised therein.

Abstract: There is provided a controller for a DC motor drive transistor which controls a parameter of a motor, the transistor being of PNP or NPN type, and the controller comprising a detection circuit, adapted to determine whether the DC motor drive transistor is of the PNP or NPN type and a driver circuit, adapted to sink current from the PNP transistor if it is determined that a PNP transistor is present, or source current into the NPN transistor if it is determined that an NPN transistor is present.

Abstract: The image sensor includes an array of pixels, each pixel having a photo-diode, for providing a pixel voltage, an analog-to-digital converter (ADC) operable to convert the pixel voltage to a digital value and a memory for storing the digital value. Read circuitry is included for reading out the digital values from the pixels of the array in a predetermined order. The image sensor may be configured such that a counter incorporates the memory, and the counter may be adapted to operate as a shift register. The counters of two or more pixels may be connected to form one or more chains such that digital values can be read out in a bit-serial manner.

Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.

Abstract: A voltage reference circuit comprising a first reference voltage source, a second reference voltage source, at least one of said first and second reference voltage sources being dependent on temperature, and first circuitry connected to at least one of said first and second reference voltage sources to provide a third reference voltage, said third reference voltage being dependent on temperature.

Abstract: The photodiode includes a substrate of a first semiconductor material and an isolating layer of a second semiconductor material. The second semiconductor material is of opposite doping character or type to the first semiconductor material. The isolating layer of the second semiconductor material is implanted with one or more wells of the first and second semiconductor materials and the substrate is separated from the isolating layer of the second semiconductor material by an epitaxial layer of the first semiconductor material.

Abstract: This invention relates to a device and method for producing a stream of data. The device receives a stream of data as an input and includes means for identifying a portion of the input stream and outputting the identified portion. The device also includes means for selecting a further portion of the input stream and outputting the selected portion. The relative timing between the two output streams is monitored and maintained with respect to the input stream.

Abstract: A processing system which comprises means for storing a plurality of items defining a queue, pointer means having a first pointer and a second pointer associated with the beginning of said queue and a second pointer associated with the back of said queue; at least one writer for adding items to said queue; at least one reader for deleting items from said queue; and means for updating said second pointer when said at least one writer adds an item to said queue, said second pointer being updated by a swap operation.

Abstract: A set-top-box has on-chip OTP memory emulated using an external flash memory and a series of on-chip fuses. The external memory is comprised of one or more regions, each having its own unique region identification. Each on-chip fuse corresponds to one of the memory regions and comprises a component which can be caused to change to a particular (blown) state irreversibly. When data first needs to be written to a region of the external memory, the identification of that region is appended to the data itself together with a parity field and a validity field. The resultant data packet is then encrypted by a cryptographic circuit using a secret key unique to the set-top-box and the encrypted data packet is written to the specified region of the external memory. Then, the on-chip fuse corresponding to the region that has been written to is irreversibly blown, effectively locking that region.

Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

Abstract: During debugging of target system by a host system, s single stack is used for an exception by a set of applications running on the processor of the target. To achieve this, the stack is dynamically loaded by the host to a reserved memory region, and a vector of the target is set to point to that reserved memory region. The exception handlers of each application then use the vector to access the stack.

Abstract: A scan chain element in an integrated circuit, the scan chain element including; a first latch connected to accept test data as an input, a second latch connected to accept the output of the first latch as an input, control logic for accepting a clock signal and a hold signal, the scan chain element being operable in a first mode such that the control logic is configured to supply the clock signal to the first latch and subsequently, in response to the hold signal, to supply the clock signal to the second latch to latch the data from the output of the first latch.