Abstract: A circuit for use in a system comprising a plurality of modules connected to an interconnect, said modules being arranged to put information onto said interconnect, said circuit comprising circuitry for determining if information on the interconnect satisfies one or more conditions; and circuitry for storing at least part of the information which satisfies the one or more conditions.
Type:
Grant
Filed:
October 1, 1999
Date of Patent:
October 2, 2001
Assignee:
STMicroelectronics, Ltd.
Inventors:
David A. Edwards, Andrew M. Jones, Anthony W. Rich
Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.