Abstract: An image sensor has an array of pixels. Each column has a first and a second column line connected to a read-reset amplifier/comparator which acts in a first mode as a unity gain buffer amplifier to reset the pixels via the first lines, and in a second mode acts as a comparator and AD converter to produce digitized reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise.

Abstract: A look-up table circuit includes address decoder circuitry that includes circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with operation of the address decoding operations. This eliminates or reduces additional circuitry required for generating the secondary functions.

Abstract: A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A lead compensator determines a compensated command to compensate for an admittance function of the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Abstract: An image sensor includes pixels which are of the four-transistor, PIN photodiode type. In each pixel, the charge on a photodiode is transferred by a transfer gate to a sensing node. Readout of reset and read voltages is via an amplifier. A gain capacitor is connected in feedback across the amplifier. Read and reset gates are controlled so that the pixel is reset to a virtual ground voltage controlled by the gain capacitor. This is independent of the pixel parasitic capacitance.

Abstract: The invention relates to monitoring error conditions in an integrated circuit. The integrated circuit has a packet router to which a plurality of functional modules are connected between which packets are transmitted. Each functional module is associated with an error monitoring register for monitoring error conditions. The error monitoring register contains a plurality of error flags which can be set when a particular error condition is detected. The invention particularly but not exclusively relates to the setting of communication error flags relating to errors in communication of the packet.

Abstract: An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion socket. The expansion socket provides a plurality of additional expansion ports to which additional functional modules can optionally be connected. All the ports connected to the packet router, including the expansion socket port, preferably lie in a common address space for the integrated circuit.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: A high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time is provided. The ROM core cell may include memory cells organized in rows and columns where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and two bit lines may be such that each of the memory cells is capable of storing four bits of data.

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence by a shift register to provide a stepped ramp output. The constant current is controlled by referencing an on-chip bandgap voltage that is used as an input to a feedback circuit controlling current through a reference resistor ladder.

Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is-connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively “deleting” the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an “even” mark space ratio.

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract: A method for efficient low power motion estimation of a digital video image is provided in which processing requirements are reduced based upon the content being processed. The method performs motion estimation of a current video image using a search window of a previous video image. The method may include forming mean pyramids of a reference macroblock and the search area and a full search at a lowest resolution. A number of candidate motion vectors (CMVs) propagated to lower levels may be dependent on a quantized average deviation estimate (QADE) of a current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. Training over a sequence may be triggered at the beginning of every sequence. This training technique may be used to determine the value of the maximum distortion band for all QADEs of the macroblocks occurring over the training frames.

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract: A computer system including at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. A method of triggering a watchpoint in a computer system is also provided.

Abstract: A method is for generating a key from the fixed pattern noise (FPN) of a CMOS image sensor to be used in generating a digital authentication signature. The key may be generated by temporarily disabling the FPN cancellation circuit that is conventionally included in the system, and generating a substantially “black” image to produce a digitized FPN signal. The key may then be generated from characteristics of the FPN, such as by comparing pairs of pixels, for example.

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract: A look-up table circuit includes address decoder circuitry that includes circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with operation of the address decoding operations. This eliminates or reduces secondary functions.

Abstract: A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs.