Patents Assigned to STMicroelectronics Pvt. Ltd.
-
Patent number: 7486110Abstract: An improved LUT based multiplexer, including a first set of muxlets, each receiving a subset of input data lines at its inputs and one or more muxlet stages cascaded together to form a tree structure in which the roots are the first set of muxlets and the last stage of muxlet produces the final output.Type: GrantFiled: September 23, 2005Date of Patent: February 3, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Naresh Kumar Bhatti, Sonia Singhal
-
Publication number: 20090027126Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).Type: ApplicationFiled: July 24, 2008Publication date: January 29, 2009Applicant: STMicroelectronics Pvt. Ltd.Inventors: Pratap Narayan Singh, Chandrajit Debnath
-
Patent number: 7483289Abstract: An improved synchronous SRAM capable of faster read-modify-write cycle time using separate input and output terminals. It describes the circuitry for performing a RMW operation in a memory module at high frequency in a nanometer technology. A byte write enable bus is incorporated into the device so as to provide the flexibility of modification and correction at selective columns, keeping rest of the columns unaltered. The termination of read operation and the triggering of write operation is done by the activation of same signal. Also described is the provision for tuning the circuitry for triggering write operation depending on the time taken by the controller to modify and revise the read-out data.Type: GrantFiled: August 2, 2005Date of Patent: January 27, 2009Assignee: STMicroelectronics PVT. Ltd.Inventor: Seema Jain
-
Patent number: 7475105Abstract: A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.Type: GrantFiled: June 15, 2005Date of Patent: January 6, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventor: Deboleena Minz
-
Publication number: 20080313480Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.Type: ApplicationFiled: March 25, 2008Publication date: December 18, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventors: Satinder Singh MALHI, Arant Agrawal
-
Conversion device for performing a raster scan conversion between a JPEG decoder and an image memory
Patent number: 7460718Abstract: The conversion device includes an input for receiving data corresponding to an image to be displayed. The received data is in a JPEG decoder output data format A processor is included for reconstructing and writing the image to be displayed into the image memory, in a display module expected input data format. The bandwidth of the image memory is greater than one byte. The processor is fully hardwired and includes a first logic stage for writing the received data byte by byte into an intermediate memory at chosen addresses such that the written data form a sequence of data in the display module expected input data format, and a second logic stage for reading the written data in the intermediate memory, forming successive packets of read data having a size corresponding to the bandwidth, and successively writing the packets into the image memory at chosen addresses such that the written packets together form all the lines of the image.Type: GrantFiled: June 17, 2005Date of Patent: December 2, 2008Assignees: STMicroelectronics SA, STMicroelectronics Pvt. Ltd.Inventors: Antoine Gautier, Mahesh Chandra -
Publication number: 20080270622Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic.Type: ApplicationFiled: March 28, 2008Publication date: October 30, 2008Applicants: STMicroelectronics Pvt. Ltd., STMicroelectronics Belgium NVInventors: Naresh Kumar Gupta, Rajat Maheshwari, Vincent Charlier, Gerrit Vermeire
-
Patent number: 7436201Abstract: An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to the value of a standby signal and an input signal. The standby signal is high in the standby mode and low in the active mode.Type: GrantFiled: December 29, 2006Date of Patent: October 14, 2008Assignee: STMicroelectronics Pvt Ltd.Inventor: Ashish Kumar
-
Patent number: 7436235Abstract: A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.Type: GrantFiled: August 2, 2004Date of Patent: October 14, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventor: Tapas Nandy
-
Patent number: 7433239Abstract: The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one of the access transistors so that the access transistors share one of the wordlines and are coupled to different bitlines. A wordline driver coupled to each wordline has the ability of generating a variable voltage at its output responsive to the wordline driver control inputs and voltage at its ground supply node. A plurality of grouped voltage supply lines are coupled to a group of the wordline drivers for inducing a variable reference voltage or ground supply at the ground supply node. A voltage switching logic switches the voltage for the variable ground supply responsive to a ground control input.Type: GrantFiled: December 30, 2005Date of Patent: October 7, 2008Assignee: STMicroelectronics PVT Ltd.Inventors: Vivek Nautiyal, Ashish Kumar
-
Publication number: 20080238505Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.Type: ApplicationFiled: December 28, 2007Publication date: October 2, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventor: Kallol Chatterjee
-
Publication number: 20080231310Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.Type: ApplicationFiled: October 20, 2007Publication date: September 25, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventors: Narayanan Vijayaraghavan, Balwant Singh
-
Patent number: 7425849Abstract: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.Type: GrantFiled: December 28, 2005Date of Patent: September 16, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventors: Ranjeet Gupta, Paras Garg
-
Publication number: 20080218151Abstract: A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage.Type: ApplicationFiled: December 26, 2007Publication date: September 11, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventor: Nitin Agarwal
-
Publication number: 20080219356Abstract: A system and method transcodes an input video bit stream having a first encoding profile into an output video bit stream having a second encoding profile. The system includes a first module (302) and a second module (306). The system further includes a memory module (304). The first module (302) decodes the input video bit stream for generating pixel data and macroblock specifications. The second module (306) encodes the pixel data and the macroblock specifications for constructing the output video bit stream. The memory module (304) includes a first buffer module and a second buffer module. The first buffer module stores the pixel data and the second buffer module stores the macroblock specifications.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventors: Sumit Johar, Ravin Sachdeva
-
Publication number: 20080218234Abstract: A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal.Type: ApplicationFiled: December 27, 2007Publication date: September 11, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventor: Abhishek Jain
-
Patent number: 7423466Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.Type: GrantFiled: April 28, 2006Date of Patent: September 9, 2008Assignee: STMicroelectronics Pvt. Ltd.Inventors: Puneet Sareen, Sashi P. Singh
-
Publication number: 20080212354Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.Type: ApplicationFiled: September 18, 2007Publication date: September 4, 2008Applicant: STMicroelectronics Pvt. Ltd.Inventors: Tanmoy Roy, Nasim Ahmad
-
Patent number: 7418031Abstract: The present invention provides an electronic device consisting of a Universal Asynchronous Receiver Transmitter (UART) having its transmit data output connected to a triggered timer and a computing means that computes the transmitted baud rate from the time measured by the timer for transmitting the known data byte.Type: GrantFiled: August 6, 2003Date of Patent: August 26, 2008Assignee: STMicroelectronics PVT. Ltd.Inventors: Mithilesh Kumar Jha, Juhee Mala
-
Patent number: 7409418Abstract: An improved Finite Impulse Response (FIR) filter is presented which provides linear scalability and implementation without the need for delay lines. A multiprocessor architecture includes a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sharing a common Instruction cache. A multi-port memory is also included. An assigning functionality assigns to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values.Type: GrantFiled: November 17, 2003Date of Patent: August 5, 2008Assignee: STMicroelectronics PVT. Ltd.Inventors: Kaushik Saha, Srijib N. Maiti