Patents Assigned to STMicroelectronics Pvt. Ltd.
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Patent number: 7689643Abstract: An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.Type: GrantFiled: October 27, 2005Date of Patent: March 30, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Tarun Kumar Vashishta, Priyanka Agarwal
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Publication number: 20100067580Abstract: Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal.Type: ApplicationFiled: September 14, 2009Publication date: March 18, 2010Applicants: STMicroelectronics Pvt. Ltd., STMicroelectronics S.r.l.Inventors: Ravin SACHDEVA, Sumit JOHAR, Emiliano Mario PICCINELLI
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Publication number: 20100061164Abstract: The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.Type: ApplicationFiled: May 12, 2009Publication date: March 11, 2010Applicant: STMicroelectronics Pvt. Ltd.Inventors: Amit Tandon, Promod Kumar, Abhishek Lal
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Patent number: 7671676Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.Type: GrantFiled: September 12, 2007Date of Patent: March 2, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Pratap N Singh, Chandrajit Debnath, Rakesh Malik
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Patent number: 7663415Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.Type: GrantFiled: January 3, 2007Date of Patent: February 16, 2010Assignee: STMicroelectronics PVT. Ltd.Inventors: Kallol Chatterjee, Nitin Agarwal
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Patent number: 7656987Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.Type: GrantFiled: December 29, 2005Date of Patent: February 2, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventor: Puneet Sareen
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Patent number: 7652535Abstract: Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.Type: GrantFiled: September 12, 2007Date of Patent: January 26, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Pratap N Singh, Chandrajit Debnath, Rakesh Malik, Ashish Kumar Sharma
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Publication number: 20100017651Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.Type: ApplicationFiled: July 6, 2009Publication date: January 21, 2010Applicant: STMicroelectronics Pvt. Ltd.Inventors: Akhil Garg, Prashant Dubey
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Patent number: 7650454Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.Type: GrantFiled: October 26, 2007Date of Patent: January 19, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Gaurav Shukla, Piyush Jain
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Patent number: 7642876Abstract: A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.Type: GrantFiled: October 28, 2005Date of Patent: January 5, 2010Assignee: STMicroelectronics PVT. Ltd.Inventor: Nitin Agarwal
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Patent number: 7642865Abstract: A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.Type: GrantFiled: December 27, 2006Date of Patent: January 5, 2010Assignee: STMicroelectronics Pvt. Ltd.Inventors: Tanmoy Sen, Anand Kumar, Deependra Kumar Jain
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Patent number: 7627705Abstract: An Interrupt Processor is provided in an embedded system to handle interrupts generated in the system. The function of the interrupt processor is to handle interrupts and execute interrupt routines. It performs code execution for interrupts which require immediate response. The other interrupts received by the interrupt processor are arranged in a queue on the basis of their respective priorities. An interrupt signal is then sent to the main processor which processes all the signals in one go. This prevents multiple and frequent switching of the main processor and hence avoids the switching overhead. Since the main processor operates at low frequency, the system consumes less power as compared to conventional systems.Type: GrantFiled: December 27, 2006Date of Patent: December 1, 2009Assignee: STMicroelectronics PVT. Ltd.Inventor: Munish Agarwal
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Patent number: 7619383Abstract: A brushless motor circuit is for driving a brushless direct current (BLDC) motor. The motor includes a rotor and exciting coils for respective phases in a three-phase winding in a star configuration. A neutral point in the star configuration is configured to switch to one of a ground voltage, a supply voltage, and an open circuit voltage to provide more combinations. The combinations provide extra steps in one revolution for a better resolution with enhanced efficiency.Type: GrantFiled: August 3, 2007Date of Patent: November 17, 2009Assignee: STMicroelectronics Pvt. LtdInventor: Kapil Singhi
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Patent number: 7619916Abstract: An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage at different nodes, when either bit ‘0’ or ‘1’ is stored in the SRAM cell. The reduced effective supply voltage is passed to other coupled transistors for minimizing leakages. The SRAM cell operates in an active mode and dissipates no dynamic power during active mode to inactive mode transition and vice-versa operations. The SRAM cell is also capable of reducing bit line leakage currents under suitable conditions.Type: GrantFiled: July 6, 2007Date of Patent: November 17, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventor: Ankur Goel
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Patent number: 7617269Abstract: An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.Type: GrantFiled: August 3, 2005Date of Patent: November 10, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventor: Hitanshu Dewan
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Patent number: 7613853Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.Type: GrantFiled: October 25, 2004Date of Patent: November 3, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Patent number: 7609090Abstract: Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuits, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operation.Type: GrantFiled: August 23, 2007Date of Patent: October 27, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Ankit Srivastava, Sourav Jandial
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Publication number: 20090265739Abstract: The present invention discloses a system and method for channel selection in a digital broadcast reception terminal. The system tunes to different frequencies and generates visual clips corresponding to a plurality of channels in a frequency band. Visual clips of multiple channels are simultaneously displayed on a display screen which provides the user an easy way to select a desired program.Type: ApplicationFiled: April 18, 2008Publication date: October 22, 2009Applicant: STMicroelectronics Pvt. Ltd.Inventors: Prabhjot Singh ARORA, Kaushik Saha
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Patent number: 7602162Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.Type: GrantFiled: November 27, 2006Date of Patent: October 13, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Nitin Bansal, Rupesh Khare, Amit Katyal
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Patent number: 7603603Abstract: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.Type: GrantFiled: May 26, 2006Date of Patent: October 13, 2009Assignee: STMicroelectronics PVT. Ltd.Inventor: Prashant Dubey