Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal.

Abstract: Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.

Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract: To provide a memory efficient method and system for statistical data accumulation and processing, data is divided into multiple data zones and divided into subgroups of memories. A separate memory bin is assigned for each of the subgroups, and this memory bin is shared between various two data zones in each subgroup for processing and accumulation. In this scheme, the histogram data in each location of the separate memory bin for the previously accumulated data zones is processed before updating the stored value for the data zone requiring data accumulation.

Abstract: A dual port static random access memory (SRAM) having dedicated read and write ports provides high speed read operation with reduced leakages. The dual port SRAM includes at least one write word line, at least one read word line, at least one pair of write bit line and read bit line, a plurality of rows and columns. Each rows and column has at least one cell which includes at least one pair of memory elements cross-coupled to form a latch for storing data, a pair of write access semiconductors and a pair of read access semiconductors. The SRAM includes an inverter circuit and a pull down circuit which are operatively coupled to the at least one cell to increase read operation performance and eliminate leakage.

Abstract: A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test algorithm. The delay generator provides a delay of an expected data, a valid signal, a BBAD signal, a BEND signal, and a BFAIL signal. The multiple interface modules provide signal pipelining for multiple memories through a bus. The bus carries signals form the BIST device to multiple memories and vice-versa. The memory wrapper decodes a selected memory for decompressing a memory data signal generated by said BIST device and further compresses a memory output signal.

Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator.

Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract: The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware.

Abstract: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT.

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: A sensing device for a data storage system may include a sensing circuit, a pull-down circuit, and a pull-up circuit. The sensing circuit may sense discharging of a desired bit line or a complementary bit line and may generate a desired output. The pull-down circuit may be coupled to the bit line and the complementary bit line for enhancing the discharging rate and may increase the sensing speed of the storage system. The pull-up circuit may control the discharging of an undesired bit line or complementary bit line.

Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level.

Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.