Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

Abstract: A microelectromechanical gyroscope includes a die of semiconductor material forming a substrate and a detection structure suspended over the substrate. The detection structure has a main extension in a horizontal plane, is symmetrical with respect to a central axis of symmetry, and is provided, for each gyroscope detection axis, with: a first pair of detection masses arranged on a first side of the central axis of symmetry; and a second pair of detection masses arranged on a second side of the central axis of symmetry, opposite to the first side in the horizontal plane. The detection masses of each pair are capacitively coupled to respective stator electrodes according to a differential detection scheme. The stator electrodes are arranged symmetrically with respect to one another on opposite sides of the central axis of symmetry.

Abstract: The present disclosure is directed to accelerometer measurement compensation for a device with first and second accelerometers. The first and second accelerometers are included in first and second components, respectively, of the device that are configured to rotate with respect to a hinge. The device detects a stuck condition of the first accelerometer, and compensates acceleration measurements of the first accelerometer by exploiting redundant information from the second accelerometer and applying a runtime calibration of undesired offsets.

Abstract: A device includes a phase change memory cell. The memory cell includes a first stack of layers including an intermediate layer of phase change material, a lower insulating layer and an upper insulating layer. The memory cell includes L-shaped first and second conductive elements. The first conductive element extends on a first side wall of the first stack. The second conductive element extends on the second side wall of the stack opposite to the first wall.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

Abstract: A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

Abstract: In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.

Abstract: The present disclosure relates to a method for authenticating instructions and operands in an electronic system comprising a controller. The method includes extracting instructions and operands via a first circuit of the controller from at least a first memory internal to the controller using a matrix bus of the controller, collecting, on the matrix bus, via a second circuit internal to the controller, instructions and operands during their transmission to the first circuit, and generating a word representative of the instructions and operands.

Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

Abstract: In an embodiment, a USB interface includes a transformer, a primary winding of the transformer, and a first switch in series between a first and a second node, a secondary winding of the transformer and a component in series between a third and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: A microfluidic dispensing device has a plurality of chambers arranged in sequence, each having an inlet receiving a liquid to be dispensed and a nozzle for emitting a drop of liquid. An actuator in each chamber receives an actuation quantity and causes a drop of liquid to be emitted by the nozzle of the respective chamber. A drop emission detection element in each chamber generates an actuation command upon detecting the emission of a drop of liquid. A sequential activation electric circuit includes a plurality of sequential activation elements, one for each chamber, each coupled to the drop emission detection element of the respective chamber and to an actuator associated with a subsequent chamber in the sequence of chambers. Each sequential activation element receives the actuation command from the drop emission detection element associated with the respective chamber and activates the actuator associated with the subsequent chamber in the sequence of chambers.

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

Abstract: A microelectromechanical accelerometer includes a microstructure, having sensing terminals and driving terminals distinct from the sensing terminals, a supporting body and a movable mass, coupled to the supporting body so as to be able to oscillate according to a sensing axis with respect to a rest position, and a control unit coupled to the microstructure so as to form a force feedback loop configured to maintain the movable mass in the rest position. The movable mass includes a sensing structure and a driving structure, respectively coupled to the sensing terminals and to the driving terminals through capacitive couplings variable as a function of displacements of the movable mass from the rest position. The sensing structure and the driving structure are electrically insulated and rigidly coupled with each other.

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

Abstract: A metasurface optic, designed for short-wave infrared (SWIR) range devices, is formed of one or more unit cells with a specific arrangement of truncated cone-shaped subwavelength nanostructures, tailored to achieve various optical functionalities. The one or more unit cells are formed from a design set selected from among multiple different design sets, each of the multiple different design sets featuring truncated cones having a unique combination of height (800 nm to 1100 nm), sidewall angle (91° to) 93°, and pitch (550 nm to 750 nm), with base radius values of the truncated cones within a given design set varying from 75 nm to 250 nm in 1 nm increments.