Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

Abstract: An electronic device includes—a semiconductor substrate having selection transistors arranged therein and a first interconnection stack including at least one level including first and second insulating layers having conductive tracks and first conductive vias defined therein. The electronic device includes a third insulating layer on the first stack and a second interconnection stack including at least one level including first and second insulating layers. The electronic device includes a plurality of memory cells arranged in the third insulating layer and at least one second conductive via extending through the entire height of the third insulating layer.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: In an embodiment, a method includes: receiving a first plurality of digital codes from a time-to-digital converter (TDC); generating a coarse histogram from the first plurality of digital codes; detecting a peak coarse bin from the plurality of coarse bins; after receiving the first plurality of digital codes, receiving a second plurality of digital codes from the TDC; and generating a fine histogram from the second plurality of digital codes based on the detected peak coarse bin, where a fine histogram depth range is narrower than a coarse histogram depth range, where a lowest fine histogram depth is lower or equal to a lowest coarse peak depth, and where a highest fine histogram depth is higher or equal to a highest coarse peak depth.

Abstract: A device and method of manufacturing a device based on heterostructure, including a work body, is provided having a wafer and an epitaxial multilayer that extends on the wafer along a direction from a front surface of the wafer up to an upper surface. To form an active area, a conduction region of conductive material is formed on the epitaxial multilayer. To form a contact region for biasing the first conduction region: a front trench is formed in the work body starting from the upper surface towards the back surface of the wafer, up to a contact surface; a conductive region is formed inside the front trench, on the contact surface, and in electrical contact with the first conduction region; a back trench is formed in the work body starting from the back surface towards the upper surface up to the contact surface; and a back metallization layer is formed on the back surface of the wafer and inside the back trench, on the contact surface.

Abstract: A first input node and a second input node are coupled to a sensing circuit element. A first transistor of a pair of differential transistors has a current flow path with a first transistor node coupled to the first input node to receive a current sensing signal and a second transistor node. A second transistor of the pair of differential transistors has a current flow path with a third transistor node coupled to the second input node to receive a current sensing signal and a fourth transistor node. An auxiliary amplifier circuit has a first auxiliary input node coupled to the second transistor node and a second auxiliary input node coupled to the fourth transistor node. An output node of the auxiliary amplifier circuit generates a control signal applied to a common control node of the pair of differential transistors.

Abstract: An electronic device, such as a smart card, includes a first secure element configured to implement a transaction in response to received data, and a second secure element configured to receive the same data as the first secure element and perform an operation which can control another electronic circuit.

Abstract: A foldable electronic device includes a first lid and a second lid rotatably coupled together by a hinge. A first inertial measurement unit (IMU) is implemented in the first lid and generates first sensor data. A second IMU is implemented in the second lid and generates second sensor data. A sensor processing unit detects the rotation angle between the first and second lids and generates rotated second sensor data by adjusting the second sensor data based on the rotation angle. The sensor processing unit generates combined sensor data by combining the first sensor data with the rotated second sensor data. The combined sensor data is more accurate than either the first sensor data or the second sensor data.

Abstract: The present description concerns an electronic circuit manufacturing method comprising, in the order, forming an opening in a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the opening positioned between the first surface and the second surface and forming an electrically-conductive pad, the electrically-conductive pad including a first portion positioned over the first surface and a second portion covering the flanks of the opening and delimiting a gap in the opening, and depositing a first layer covering the electrically-conductive pad and filling the gap, the first layer containing a first resin, the first resin being non-photosensitive, and crosslinking the first resin in the first layer, and chemically etching by plasma the first layer to delimit a first block of the first resin in the gap, and depositing a first protection layer on the first block.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: A voltage conversion system provides gain and offset trimming for generating a controlled output voltage. The system includes a digital-to-analog converter (DAC) that generates a reference voltage based on an input code, and a voltage converter that converts an input voltage to an output voltage based on the reference voltage. A first adjustable reference circuit provides a first reference signal to the DAC and a second adjustable reference circuit provides a second reference signal to the DAC. Control circuitry adjusts the first adjustable reference circuit to perform gain trimming of the output voltage and adjusts the second adjustable reference circuit to perform offset trimming of the output voltage. A calibration procedure includes adjusting for both gain and offset, with a two-step approach for positive offset conditions—first incrementing the input code to create a negative offset, then performing offset trimming.

Abstract: The present description concerns a bus error management method, wherein one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge, are stored, and wherein in the presence of a bus error sent by the functional unit: one or a plurality of second characteristics linked to said error are stored; the bridge generates a first interrupt that it transmits with said first and second characteristics to a management unit; and the management unit generates at least one second interrupt intended for a processing unit as a function of the first and/or second characteristics.

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A control module is used to control a switching buck-boost converter that includes an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch and a diode coupled to the second top switch. The control module controls the switching buck-boost converter so as to alternate: first time periods, in which the second top switch is open and cycles of charge and discharge of the inductor are carried out, during which the inductor is traversed by a current that also passes through the diode and charges the capacitor; and second time periods, in which the first and second top switches are open and the first and second bottom switches are closed so that the current in the inductor recirculates, and the capacitor is discharged by a current that flows in the load.

Abstract: In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

Abstract: A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.