Abstract: A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.

Abstract: In an embodiment, a voltage converter is configured to operate by a succession of operating cycles, each cycle comprising an energy accumulation phase and an energy restitution phase, wherein the converter is further configured to determine a duration of one of the phases by comparing a voltage ramp and a first reference voltage, and wherein a slope of the voltage ramp depends on a sign of a current in an inductor at an end of a previous operating cycle.

Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: A PMUT device includes a membrane element adapted to generate and receive ultrasonic waves by oscillating, about an equilibrium position, at a corresponding resonance frequency. A piezoelectric element is located over the membrane element along a first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. A damper is configured to reduce free oscillations of the membrane element, and the damper includes a damper cavity surrounding the membrane element, and a polymeric member having at least a portion over the damper cavity along the first direction.

Abstract: According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.

Abstract: Disclosed herein is a DC-DC converter, including a high-side power switch coupled between an input voltage and a switched node and a low-side power switch coupled between the switched node and ground. An inductor is coupled between the switched node and an output node. An output capacitor is coupled between the output node and ground. A control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary on-time of the high-side power switch to maintain a constant amount of charge being transferred to the output capacitor during each charging cycle, independent of variation of the input voltage.

Abstract: A method configures a memory for use in executing an application. The configurating the memory includes defining a set of virtual memory resources associated with one or more contiguous memory areas of the memory. Contiguous virtual memory resources of the set of virtual memory resources are selectively merged based on respective security attributes of the virtual memory resources of the set of virtual memory resources, generating a merged set of virtual memory resources. A security attribute assigned to a virtual memory resource indicates the virtual memory resource is a secure memory resource, a non-secure memory resource, or a non-secure callable memory resource. Configuration information indicative of the merged set of virtual memory resources is stored for use in executing the application.

Abstract: Electrically insulating material is molded onto a sculptured, electrically conductive leadframe structure that includes a pattern of electrically conductive formations such as a die mounting location configured to have at least one semiconductor die arranged thereon, a dummy pad and a tie bar extending between the die mounting location and the dummy pad. A pre-molded leadframe structure results from the electrically insulating material penetrating into spaces between electrically conductive formations in the pattern of electrically conductive formations. At least one portion of the tie bar extending between the die mounting location and the dummy pad is removed to electrically decouple the dummy pad from the die mounting location.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: A semiconductor die is mounted on a substrate having electrically conductive substrate portions. The electrically conductive substrate portions include a die mounting location and electrically conductive leads around the die mounting location. The semiconductor die is mounted on a first surface of the die mounting location. The substrate and the semiconductor die are encapsulated in an electrically insulating encapsulation having a surface opposite the first surface. An electrically conductive path is provided to electrically couple the semiconductor die to one of the electrically conductive substrate portions.

Abstract: A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

Abstract: A method includes coupling an electric motor in a hard disk drive to a set of driver circuits. Each driver circuit includes a high-side switch and a low-side switch. The high-side switch has a high-side current flow path between a supply node coupled to a supply voltage and a switching node coupled to a winding of the electric motor. The low-side switch has a low-side current flow path between the switching node and ground. Respective conduction currents are generated through the low-side current flow paths, in response to a command to reduce the motor speed by coupling a drive voltage to the control terminals of the low-side switches. An intensity of at least one of the respective conduction currents is sensed. In response to the sensed current intensity exceeding a current intensity threshold, the control terminals of the low-side switches are coupled to respective ones of the switching nodes.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

Abstract: An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.

Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.

Abstract: A device includes an optical integrated circuit device mounted over an upper surface of a support substrate. The optical integrated circuit device includes an optical sensor array supported by a semiconductor substrate made of a first semiconductor material. A discrete semiconductor block, made of a second semiconductor material, is mounted over an upper surface of the optical integrated circuit device adjacent the optical sensor array. The first and second semiconductor materials have substantially matched coefficients of thermal expansion. A parallelpipedal-shaped optical filter is mounted over an upper surface of the discrete semiconductor block and extends over the optical sensor array. One or more edges/corners of the parallelpipedal-shaped optical filter cantilever over the optical sensor array without any provided support.

Abstract: A MEMS actuator includes a semiconductor body with a first surface defining a housing cavity facing the first surface and having a bottom surface, the semiconductor body further defining a fluidic channel in the semiconductor body with a first end across the bottom surface. A strainable structure extends into the housing cavity, is coupled to the semiconductor body at the bottom surface, and defines an internal space facing the first end of the fluidic channel and includes at least a first and a second internal subspace connected to each other and to the fluidic channel. When a fluid is pumped through the fluidic channel into the internal space, the first and second internal subspaces expand, thereby straining the strainable structure along the first axis and generating an actuation force exerted by the strainable structure along the first axis, in an opposite direction with respect to the housing cavity.

Abstract: In an embodiment a method includes receiving, at an input of a low-voltage section of a gate driver, a PWM control signal with a switching frequency, providing, at an output of a high-voltage section of the gat driver, a gate-driving signal as a function of the PWM control signal to a power stage, wherein the high-voltage section is galvanically isolated from the low-voltage section, receiving, at a feedback input of the high-voltage section, at least one feedback signal indicative of an operation of the power stage, converting, at an ADC module of the high-voltage section, the feedback signal into a digital data stream, providing, to the ADC module, a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal and sending, via an isolation communication channel between the low-voltage section and the high-voltage section, the digital data stream to the low-voltage section.

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.