Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

Abstract: A method for transmission of monochrome video data of a monochromatic image, wherein three different source monochromatic pixels are encoded by a transmitting device into one compressed three-color pixel; the compressed three-color pixel are transmitted by the transmitting device. The transmitted compressed three-color pixel are received at a receiving device; and the compressed three-color pixel decoding are decoded by the receiving device into three different sink monochromatic pixels. The transmitting device acquires the three different source monochromatic pixels, extracts a single-color value from each of the three different source monochromatic pixels, and generates the compressed three-color pixel using the single-color values extracted from the three different source monochromatic pixels.

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.

Abstract: A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.

Abstract: A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width.

Abstract: A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

Abstract: An electronic device includes a modulator-demodulator circuit, a first integrated circuit for implementing a first subscriber module; and a second integrated circuit for implementing a second subscriber identification module. A data transmit-receive terminal of the first integrated circuit and a data transmit-receive terminal of the second integrated circuit are connected to a data transmit-receive terminal of the modulator-demodulator circuit. Reset terminals of the modulator-demodulator circuit and the first integrated circuit are connected so that the modulator-demodulator circuit can control deactivation of the first integrated circuit. A reset terminal of the second integrated circuit and an input/output terminal of the first integrated circuit are connected so that the first integrated circuit can control deactivation of the second integrated circuit.

Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

Abstract: A microelectromechanical device includes a fixed structure having a frame defining a cavity, a tiltable structure elastically suspended above the cavity with main extension in a horizontal plane, a piezoelectrically driven actuation structure which can be biased to cause a desired rotation of the tiltable structure about a first and second rotation axes, and a supporting structure integral with the fixed structure and extending in the cavity starting from the frame. Lever elements are elastically coupled to the tiltable structure at a first end by elastic suspension elements and to the supporting structure at a second end by elastic connecting elements which define a lever rotation axis. The lever elements are elastically coupled to the actuation structure so that their biasing causes the desired rotation of the tiltable structure about the first and second rotation axes.

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: A MEMS (MicroElectroMechanical System) device includes: a supporting body; a movable mass, constrained to the supporting body by flexures so as to be able to oscillate in a main direction; an actuator device, configured to apply to the movable mass an electrostatic actuation force, transverse to the main direction; and a control circuit configured to detect stiction conditions, in which the movable mass is stuck to the supporting body by a stiction force, and for driving the actuator device in response to recognition of the stiction conditions. The actuation force is a variable force with an actuation frequency band containing at least one resonance frequency in a direction transverse to the main direction of a mechanical system comprising the movable mass stuck to the supporting body.

Abstract: An in-memory computation (IMC) system includes an in-memory computation circuit formed by a first phase change memory (PCM) array configured to store the computational weights for an in-memory computation operation. A data storage circuit is formed by a second PCM array configured to store backup data for the computational weights for the in-memory computation operation. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. A control circuit operates to read the backup data from the second PCM array and write to the first PCM array to refresh the computational weights for the in-memory computation operation from the backup data.

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

Abstract: An integrated circuit package includes an integrated circuit die. The integrated circuit die includes core circuitry implemented in one or more layers of semiconductor material, a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry, a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry, a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster, and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry. The integrated circuit package includes a passivation layer on the integrated circuit die and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

Abstract: First signal processing is applied to a first input signal oscillating at an input frequency and a first set of control signals to generate a first output signal oscillating at a multiple of the input frequency with an amplitude controlled by a control signal in the first set of control signals. Second signal processing is applied to a second input signal oscillating in quadrature at the input frequency and a second set of control signals to generate a second output signal that oscillates at the multiple of the input frequency with an amplitude controlled by a control signal in the second set of control signals. A further output signal, generated in response to the first and second output signals, oscillates at the multiple of the input frequency with a phase shift controlled by a ratio of control signal amplitudes for the first and second sets of control signals.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.