Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

Abstract: Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

Abstract: The present description concerns a circuit configured to perform a multiply and accumulate operation in a layer of an artificial neural network, the operation taking, as an input, an input data value and a weight, and wherein the weight only has a value within a limited set only formed of value 0, of a plurality of values equal to 2n, where n is an integer, and of a plurality of values, each equal to the product of 2n by an odd number greater than or equal to 3.

Abstract: An embodiment method comprises applying domain transformation processing to a time-series of signal samples, received from a sensor coupled to a dynamical system, to produce a dataset of transformed signal samples therefrom, buffering the transformed signal samples, obtaining a data buffer having transformed signal samples as entries, computing statistical parameters of the data buffer, producing a drift signal indicative of the evolution of the dynamical system as a function of the computed statistical parameters, selecting transformed signal samples buffered in the data buffer as a function of the drift signal, applying normalization processing to the buffered transformed signal samples, applying auto-encoder artificial neural network processing to a dataset of resealed signal samples, and producing a dataset of reconstructed signal samples and calculating an error of reconstruction.

Abstract: In an embodiment an apparatus includes a contactless transponder including a contactless interface and a wired interface, wherein the contactless transponder is configured to communicate with a contactless reader according to a contactless protocol through the contactless interface, a wired communication bus connected to the wired interface and at least one module connected to the bus, wherein the transponder is configured so that the reader is a master on the bus when the reader and the transponder communicate.

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

Abstract: In an embodiment an apparatus includes a scanning photographic sensor configured to acquire an image, according to an integration time of the sensor, of a scene illuminated with periodically emitted light pulses by a source, so that the image has a regular succession of bands with different luminosities when the integration time of the sensor is different from a period of the light pulses, a processor configured to generate a signature vector representative of the regular succession of bands with different luminosities being present in the image acquired by the photographic sensor, wherein the signature vector is independent of a reflectance of an objects of the scene and of a level of light in the scene, determine a frequency of the bands in the image on basis of the generated signature vector and determine the period of the pulses of the source on basis of the determined frequency of the bands in the image, and a controller configured to adjust the integration time of the photographic sensor so that the int

Abstract: A method includes: displaying, an image on a display by sequentially displaying a plurality of frames of the image, the plurality of frames including a first frame and second frame; performing a first noise sampling scan at a plurality of frequencies at a first time location within a first frame; determining a first frequency from the plurality of frequencies with the lowest noise; performing a first mutual sensing scan at the first frequency; performing, a second noise sampling scan at the plurality of frequencies at a second time location within a second frame of the plurality of frames, the second time location being a different frame location than the first time location; determining a second frequency from the plurality of frequencies with the lowest noise, the second frequency being different from the first frequency; and performing, a second mutual sensing scan at the second frequency.

Abstract: Disclosed herein is an optical module including a substrate, with an optical detector, laser emitter, and support structure being carried by the substrate. An optical layer includes a fixed portion carried by the support structure, a movable portion affixed between opposite sides of the fixed portion by a spring structure, and a lens system carried by the movable portion. The movable portion has at least one opening defined therein across which the lens system extends, with at least one supporting portion extending across the at least one opening to support the lens system. The optical layer further includes a MEMS actuator for in-plane movement of the movable portion with respect to the fixed portion.

Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

Abstract: A time-to-digital converter (TDC) circuit with self-testing function includes: a D flip-flop, where an input terminal of the D flip-flop is configured to be coupled to a data signal, and a clock terminal of the D flip-flop is configured to be coupled to a clock signal; and an AND gate, where a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop.

Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.

Abstract: A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.

Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.

Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.