Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

Abstract: A method for forming a nanotube/nanofiber growth catalyst on the sides of portions of a layer of a first material, comprising the steps of depositing a thin layer of a second material; opening this layer at given locations; depositing a very thin catalyst layer; depositing a layer of the first material over a thickness greater than that of the layer of the second material; eliminating by chem./mech. polishing the upper portion of the structure up to the high level of the layer of the second material; and eliminating the second material facing selected sides of the layer portions of the first material.

Abstract: A method is provided for reading a captured image, with the captured image comprising at least first and second parts and a border area positioned between the first and second parts. Converted pixels are obtained by applying digital-to-analog conversion to the pixels in the captured image, and the converted pixels corresponding to the border area of the captured image are stored in a buffer. A first set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the first part of the image and to the converted pixels stored in the buffer, and a second set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the second part of the image and to the converted pixels stored in the buffer. A processed image is provided by combining the first and second sets of processed pixels. Also provided is a processing device for reading a captured image.

Abstract: A frequency transposition device including an input terminal for receiving an incident signal SI and a modulator of the one-bit delta-sigma type MDU connected to the input terminal. A generator MGN provides a periodic auxiliary signal SAX with a frequency equal to a desired transposition frequency. A frequency transposer of the Gilbert cell type has a signal input BES connected to the output of the generator, a control input BCO connected to the output of the delta-sigma modulator MDU, and an output BS delivering a transposed signal STR.

Abstract: A stackable semiconductor package includes a board having first electrical connections, an integrated circuit chip fixed on a front face of the board, second electrical connections which connect the chip to the first electrical connections of the board and front electrical contact terminals arranged beyond at least one edge of the chip on the front face of this board. An encapsulation block of a coating material is formed on the front face of the board and encapsulates the chip, its electrical connections and the front terminals. The block has at least one opening which at least partially uncovers the front terminals with a view to receiving electrical connection beads of a stacked second package. This one opening is preferably in the form of a groove.

Abstract: An interface communicates between two communication buses which use at least two different protocols. The interface includes a volatile memory having at least two access ports and including two transcoding circuits, each transcoding circuit being specific to each of the protocols to be interfaced.

Abstract: An integrated circuit is produced to include interconnection levels each incorporating a metallization level covered with an insulating material. The integrated circuit includes at least one capacitor possessing at least one part lying within a single interconnection level. The capacitor is produced before the interconnection level is produced. The covering of part of the capacitor with an insulating protective layer occurs before the metallization level of the interconnection level is produced.

Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

Abstract: A method produces a microstructure comprising an island of material confined between two electrodes forming barriers, the island (30) of material having lateral flanks running parallel to and lateral flanks running perpendicular to the barriers, wherein the lateral flanks of the island are defined by etching of at least one layer (16), called the template layer, and the barriers are formed by damascening. The method includes (a) a first etching of the template layer using a first etching mask having at least one filiform part, and (b) a second etching of the template layer, subsequent to the first etching, using a second etching mask also having at least one filiform part, oriented in a direction forming a non-zero angle with a direction of orientation of the filiform part of the first mask, in the vicinity of the site of formation of the island.

Abstract: A MOS transistor with a deformable gate formed in a semiconductor substrate, including source and drain areas separated by a channel area extending in a first direction from the source to the drain and in a second direction perpendicular to the first one, a conductive gate beam placed at least above the channel area extending in the second direction between bearing points placed on the substrate on each side of the channel area, and such that the surface of the channel area is hollow and has a shape similar to that of the gate beam when said beam is in maximum deflection towards the channel area.

Abstract: The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug.

Abstract: An electronic element having a carrier with an electrically conductive plane. A flipped chip die is mounted on the carrier, the flipped chip die having a backside opposite to a front side directed towards the carrier. The electronic element also has an electromagnetic interference shield with an electrically conductive means that electrically connects an electrically conductive layer of the backside of the flipped chip die to the conductive plane of the carrier.

Abstract: The method is for regulating the supply voltage of a load via a switching voltage regulator having an inductor driven by at least a power switch for delivering current to an output capacitor having a certain parasitic series resistance, connected between the output node of the regulator and ground and to an electric load eventually connected in parallel to the output capacitor. The method includes establishing a reference voltage, generating a comparison signal as the sum of a first voltage signal proportional to the current circulating in the inductor and of a second voltage signal depending on the difference between the output voltage and the reference voltage and on the first voltage signal. The comparison signal is compared with at least a threshold for generating a logic signal that switches between an active state and an inactive state and viceversa each time that the threshold is crossed, and the turn on or the turn off of the switch is controlled as a function of the state of the logic signal.

Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.

Abstract: A voltage regulator includes a regulation MOS transistor with low serial resistance having a first terminal connected to a voltage source and a second terminal connected to the output of the voltage regulator and an amplifier having an output driving a gate of the transistor. The gate is driven based upon a difference between a reference voltage and a feedback voltage. The regulator may also include an anti-overshoot switch with a first terminal connected to the gate of the regulation MOS transistor and a second terminal is taken to a potential for turning the regulation MOS transistor off. A switch controller closes the switch when the output voltage of the regulator is higher than a first threshold. The first threshold may be higher than the nominal value of the output voltage.

Abstract: The invention relates to a plastic package for an integrated electronic semiconductor device to be encapsulated within a plastic body, the plastic bodyes formed using the step of molding said plastic body so as to fully enclose a semiconductor element, on which an integrated electronic circuit has been formed and which is placed onto a metal leadframe connected electrically to said integrated electronic circuit and carrying a plurality of terminal leads for external electric connection. To compensate the outward bends uncontrollably undergone by the plastic body due to thermal stresses during the molding step, a mold is used which has a cavity delimited by perimeter walls which define a concave-shaped volume. Preferably, at least one of the large walls, a bottom wall and a top wall, has a curvature inwardly of said mold. cavity. The curvature values are predetermined to compensate any outward curvature undergone by corresponding surfaces of said plastic body during the molding step.