Abstract: A zoom lens system includes a variator lens group, a compensator lens group and a third lens group. The compensator lens group is arranged to only partially compensate for movement of the variator group. In order to provide further compensation for the zoom lens, an image enhancer implement wavefront coding and artifact reduction techniques. The compensator group may be fixed or alternatively, its movement relative to the variator may be effected by a simple cam mechanism.

Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.

Abstract: A system for processing a received signal having at least one code applied thereto, the received signal having a frequency, the system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein the first code and the second code are different; and processor for processing together the outputs of the first and second correlator circuitry to cancel the frequency.

Abstract: An integrated circuit, method of making an integrated circuit and method of addressing peripherals of an integrated circuit are disclosed for preventing copied software from running on unauthorized hardware. A permanent key is embedded in the integrated circuit and used to transform a peripheral access address output by a processor of the integrated circuit. The transformed access address is supplied to a peripheral address decoder f the integrated circuit, which allows the processor to access a corresponding peripheral. A method of supplying integrated circuits to prevent copied software from running on unauthorized hardware is also disclosed.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors for correlated double sampling, and a comparator circuit. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential amplifier having one input connected to the junction of the two capacitors and another input connected to a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential amplifier as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast.

Abstract: Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first circuit arranged to receive a first set of the plurality of partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of term bits for the at least one compression column and all of the first combined term bit set.

Abstract: An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of bit length of 2m bits or less; an addition circuit having 2m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said in columns at a bit position to cause said result to be rounded.

Abstract: A lens barrel is mated with a lens mount through use of a screw thread whereby relative rotation adjusts lens focus. The lens barrel and lens mount are additionally provided with an interengaging formation that is interposed between an optical axis of the lens barrel and the screw thread. This formation provides a cylindrical sliding contact which isolates any particles produced by operation of the screw thread from reaching the optical components at or near the optical axis.

Abstract: PSF coding has become well known in recent years. Although it enables significant increases in the depth of field, defocus introduces artifacts in images that are a major detraction from the final image quality. A method is described that enables the deduction or defocus and consequently the removal of these artifacts. The principle of the disclosed techniques involves iteratively adjusting the restoration algorithm according to a chosen image metric and choosing the defocus parameter that yields the image the lowest level of artifact.

Abstract: A method of processing image data produced by a solid state image sensor that is overlaid with a color filter array is based on range scaling, demosaicing, matrixing, range clipping and gamma correction being performed in two data collection passes. The demosaicing can be performed with pixels grouped in 2×2 blocks, or quads.

Abstract: An optical rotary encoder uses polarization difference imaging techniques to calculate an angle of orientation of a rotatable member. The optical rotary encoder includes a light source, a polarization sensor that has a polarizer and image sensing structure, and a polarizer disk fixed between to the rotatable and interposed between the light source and the polarization sensor.

Abstract: Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.

Abstract: An integrated circuit, method of making an integrated circuit and method of addressing peripherals of an integrated circuit are disclosed for preventing copied software from running on unauthorised hardware. A permanent key is embedded in the integrated circuit and used to transform a peripheral access address output by a processor of the integrated circuit. The transformed access address is supplied to a peripheral address decoder f the integrated circuit, which allows the processor to access a corresponding peripheral. A method of supplying integrated circuits to prevent copied software from running on unauthorized hardware is also disclosed.

Abstract: Combination circuitry for combining a plurality of multi-bit partial product terms includes at least one stage arranged to receive a first number of input bits. At least one stage includes at least one combiner having: a first logic device comprising an input arranged to receive a first set of the first number of input bits and an output arranged to output a first combined result; a second logic device comprising a first input arranged to receive a second set of the first number of input bits, a second input connected to receive the first combined result, a first output arranged to output a second combined result, and a second output arranged to output a first combined bit group; and a third logic device comprising an input connected to receive the second combined result and an output arranged to output a second combined bit group, whereby the first combined bit group is available for a further stage of the combination circuitry before the second combined bit group.

Abstract: Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first circuit arranged to receive a first set of the plurality of partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of term bits for the at least one compression column and all of the first combined term bit set.

Abstract: An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of varying bit length of m bits or less; an addition circuit having m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said m columns at a bit position to cause said result to be rounded.

Abstract: A system for processing a received signal having at least one code applied thereto, said received signal having a frequency, said system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein said first code and said second code are different; and processing means for processing together the outputs of said first and second correlator circuitry to cancel said frequency.