Abstract: Disclosed is an energy autonomous system including an energy transducer, a first capacitor, a second capacitor having greater capacitance than the first capacitor, and a microprocessor. The microprocessor includes a first terminal electrically coupled to the energy transducer and the first capacitor; a second terminal electrically coupled to the second capacitor; a switch that is in a conductive state in which the switch electrically couples the first terminal and second terminals together, or a nonconductive state in which the switch does not electrically couple first terminal and second terminals together; a voltage detector that detects a voltage at the first terminal; and a processor coupled to the voltage detector and the switch. The processor controls charging of the second capacitor by controlling the switch to be in the conductive state or the nonconductive state based on the voltage at the first terminal detected by the voltage detector.

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Abstract: A support substrate has a mounting face and a connection face opposite to the mounting face. An electronic chip is mounted to the mounting face and a matrix of connectors is mounted to the connection face. The support substrate includes an interconnection structure formed by a pair of conductive interconnection tracks that electrically connect the electronic chip to the matrix of connectors and circulate differential signals. The two interconnection tracks of the pair of conductive interconnection tracks extend facing each other at different depths of the support substrate. An isolation structure in the support substrate laterally isolates the pair of conductive interconnection tracks. Isolation plates above and below the pair of conductive interconnection tracks provide further isolation.

Abstract: A three-phase load is powered by an SPWM driven inverter having a single shunt-topology. During operation, drain-to-source resistances of transistors of each branch of the inverter are determined. Interpolation is performed on assumed drain-to-source resistances of the transistors for different temperatures to produce a non-linear model of drain-to-source resistance to temperature for the transistors, and the drain-to-source resistances determined during operation and the non-linear model are used to estimate temperature values of the transistors. Driving of the inverter can be adjusted so that conductivity of each branch is set so that power delivered by that branch is as high as possible without exceeding an allowed drain current threshold representing a threshold junction temperature. In addition, driving of the inverter can be ceased if the temperature of a transistor exceeds the threshold temperature.

Abstract: A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).

Abstract: A half bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half bridge includes hand and low side switches. A comparator generates a PWM signal for controlling the converter as a function of the duty cycle of the PWM signal in response to a signal at an intermediate node between the hand and low side switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM signal irrespective of converter operation.

Abstract: A circuit for reverse battery protection includes an isolation circuit and a control circuit. The isolation is circuit coupled between a gate output of an electronic fuse (E-fuse) and at least one external metal-oxide-semiconductor field-effect transistor (MOSFET). The E-fuse is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller. The isolation circuit is configured to disconnect the gate output from the at least one external MOSFET when the battery is installed with reverse polarity. The control circuit is coupled between the external ground pin and the at least one external MOSFET. The control circuit is configured to turn on the at least one external MOSFET when the battery is installed with the reverse polarity.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Abstract: A transistor device comprising a silicon-on-insulator (SOI) substrate having a plurality of polysilicon gates including a plurality of recessed gates and a plurality of non-recessed gates. The plurality of recessed gates being recessed in a top silicon layer of the SOI substrate and the plurality of non-recessed gates being on the top silicon layer. The plurality of recessed gates comprising an upper cap portion on a bottom buried portion that is in a recess of the SOI substrate. Methods of manufacturing the device are provided.

Abstract: An electronic circuit includes a first die, having a GaN transistor, and a second die, stacked so that an element of the second die electrically connects a first node and a second nodes of the first die respectively coupled to a conduction node and to a control node of the GaN transistor.

Abstract: A device of contactless communication by active load modulation includes a receive circuit configured to receive as an input a reception signal originating from a magnetic field intended to be received by an antenna. A transmit circuit has an output coupled to the antenna with a modulation signal in phase with the reception signal intended to be delivered thereon. A circuit compensates for a delay of the modulation signal due to the transmit circuit and to the amplitude of the reception signal. The compensation circuit determines a phase-shift value to be applied to an input signal of the transmit circuit to compensate for the delay.

Abstract: Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

Abstract: A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes output nodes generating first and second bandgap reference currents. A transconductance amplifier circuit in a current control feedback loop of the bandgap voltage generator circuit has differential inputs which receive base currents. A differential amplifier circuit has inputs configured to receive the first and second bandgap reference currents and includes a compensation current sink circuit configured to sink compensation currents from the first and second bandgap reference currents which correspond to the base current received at the differential inputs of the transconductance amplifier circuit.

Abstract: The present description concerns a correction circuit for a bandgap circuit comprising a first bipolar transistor and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stable DC voltage based on the first and second bipolar transistors, the correction circuit being configured to generate a correction current equal to a difference in the base currents of said first and second transistors, and inject the correction current on the emitter of one of said first and second bipolar transistors to correct an error on the temperature-stable voltage resulting from a current gain difference between said first and second bipolar transistors.

Abstract: A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated. A transconductance amplifier circuit in a current control feedback loop has a differential input which receives a base current. A compensation current sink circuit operates to sink a compensation current from the output node corresponding to the base current received at the differential input of the transconductance amplifier.

Abstract: A MEMS metamaterial has a substrate and a suspended structure having an elementary cell which extends at a distance from the substrate along a first direction. The elementary cell has a first structural region having a first material with a first coefficient of thermal expansion. The first structural region has a first side facing the substrate and a second side opposite to the first side. The elementary cell also has a second structural region having a second material different from the first material and with a second coefficient of thermal expansion different from the first coefficient of thermal expansion. The second structural region extends on at least part of the first structural region, on the first side, the second side, or both the first and second side of the first structural region.