Patents Assigned to STMicroelectronics (Research & Development) Ltd.
  • Patent number: 12008061
    Abstract: The present disclosure relates to a method for communicating between an electronic tag and a computer connected to the internet, wherein the electronic tag: encrypts at least part of the information to be transmitted, using a data format preserving algorithm; generates a URL comprising at least the encrypted part of the information; and transmits the URL to an NFC reader.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Remi Buisson, Sophie Maurice
  • Patent number: 12009830
    Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Vikram Singh
  • Patent number: 12008200
    Abstract: A method for operating a touch sensing panel includes a touchscreen controller determining a first plurality of excitation signals in accordance with a first plurality of codes, wherein a sum of the first plurality of codes is a sequence of numbers having a same absolute value and signs alternating between adjacent numbers in the sequence of numbers. The method further includes the touchscreen controller transmitting each of the first plurality of excitation signals to a respective transmitting (TX) touch sensor of the touch sensing panel simultaneously during a first time frame. The method further includes the touchscreen controller determining touch strengths in accordance with a first plurality of output signals received by a plurality of receiving (RX) touch sensors of the touch sensing panel during the first time frame.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics International N.V.
    Inventor: Kien Beng Tan
  • Patent number: 12007521
    Abstract: A detection method of a user of an apparatus is provided in which the apparatus is coupled to a charge variation sensor having a control unit and an electrode to detect an electric/electrostatic charge variation of the user. The detection method includes acquiring, through the electrode, a charge variation signal indicative of the presence of the user. A filtered signal is generated by filtering the charge variation signal. A feature signal is generated as a function of the filtered signal. A movement signal indicative of a movement of the user is generated as a function of the feature signal. A presence signal indicative of the presence of the user is generated as a function of the movement signal.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Rizzardini, Lorenzo Bracco
  • Patent number: 12009572
    Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 11, 2024
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Romain Coffy, Georg Kimmich
  • Publication number: 20240186991
    Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.
    Type: Application
    Filed: February 15, 2024
    Publication date: June 6, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Manoj Kumar TIWARI, Saiyid Mohammad Irshad RIZVI
  • Publication number: 20240186318
    Abstract: An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 6, 2024
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Joel METZ, Brice ARRAZAT
  • Publication number: 20240186679
    Abstract: A waveguide has a first input/output for receiving/outputting a radio frequency (RF) wave and guiding the RF wave between the first input/output and a second input/output. An electronic integrated circuit chip is electrically connected at a front face to a metal level of a carrier substrate which includes a patch antenna. An electrically insulating embedding material surrounds the electronic chip and is disposed between the patch antenna and the first input/output of the waveguide which is at least in contact with the embedding material. The electronic chip cooperates electrically with the patch antenna so as to cause the patch antenna to transmit the RF wave to the first input/output through the embedding material. The electronic chip also processes an electrical signal from the patch antenna in response to the patch antenna receiving the radio frequency wave output by the first input/output via the embedding material.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 6, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Romain COFFY, Laurent SCHWARTZ, Ludovic FOURNEAUD
  • Publication number: 20240186090
    Abstract: The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.
    Type: Application
    Filed: March 30, 2023
    Publication date: June 6, 2024
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Philippe CATHELIN, Frederic GIANESELLO, Alain FLEURY, Stephane MONFRAY, Bruno REIG, Vincent PUYAL
  • Publication number: 20240186195
    Abstract: An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 6, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Laurent HERARD, Olivier ZANELLATO, Patrick LAURENT
  • Publication number: 20240186834
    Abstract: A wireless electronics device includes an energy storage device for storing electrical energy. A frequency detection circuit detects whether a received radio frequency signal is in a first frequency range or in a second frequency range, the first and second frequency ranges being non-overlapping. A first communications circuit transmits a first return signal if the radio frequency signal is in the first frequency range and establishes wireless charging of the energy storage device according to a first protocol. A second communications circuit transmits a second return signal if the radio frequency signal is in the second frequency range and establishes wireless charging of the energy storage device according to a second protocol.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 6, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Rene WUTTE
  • Publication number: 20240183745
    Abstract: A device for testing an optical device, comprising a first structure comprising a substrate made of a first material and at least two first pillars of cylindrical shape made of a second material crossing the substrate, the second material having an optical index different from the optical index of the first material.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephanie AUDRAN, Elodie SUNGAUER, Simon GUILLAUMET
  • Publication number: 20240186198
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Michele DERAI
  • Publication number: 20240186236
    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Patent number: 12003177
    Abstract: A switching regulator circuit has a high side (HS) transistor actuated during on time (TON) of a duty cycle. The output current of the switching regulator circuit is determined from sensing a transistor current flowing through the HS transistor during HS transistor on time (TON) and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. The duty cycle is determined from a ratio of the on time (TON) and off time (TOFF) of the switching regulator circuit.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 4, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco La Pila, Giuseppe Platania
  • Patent number: 12001012
    Abstract: Disclosed herein is a microelectromechanical (MEMS) device, including a rotor and a first piezoelectric actuator mechanically coupled to the rotor. The first piezoelectric actuator is electrically coupled between a first signal node and a common voltage node. A second piezoelectric actuator is mechanically coupled to the rotor, and is electrically coupled between a second signal node and the common voltage node. Control circuitry includes a drive circuit configured to drive the first and second piezoelectric actuators, a sense circuit configured to process sense signals generated by the first and second pizeoelectric actuators, and a multiplexing circuit. The multiplexing circuit is configured to alternate between connecting the drive circuit to the first piezoelectric actuator while connecting the sense circuit to the second piezoelectric actuator, and connecting the drive circuit to the second piezoelectric actuator while connecting the sense circuit to the first piezoelectric actuator.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 4, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Ltd
    Inventors: Davide Terzi, Gianluca Mendicino, Dadi Sharon
  • Patent number: 12004432
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: June 4, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Roberto Simola, Yohann Moustapha-Rabault
  • Patent number: 12003247
    Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 4, 2024
    Assignee: STMicroelectron S.r.l.
    Inventor: Francesco Stilgenbauer
  • Publication number: 20240176864
    Abstract: An electronic device includes a debug port providing a communications interface for debugging purposes, a plurality of processing unit access ports, an authentication interface circuit configured to authenticate the external device, and a further access port coupled between the debug port and the authentication interface circuit. The further access port is configured to be in an open state in which communications are relayed between the debug port and the authentication interface circuit. The authentication interface circuit has registers including a status register capable of being read by the external device via the debug port and the further access port, the status register being configured to store an indication of the open or closed state of each of the processing unit access ports.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Xavier CHBANI, Nadia VAN-DEN-BOSSCHE
  • Publication number: 20240178823
    Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 30, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Joran PANTEL, Daniel OLSON