Patents Assigned to STMicroelectronics (Rousset) SAS
  • Imaging device with filtering of the infrared radiation
    Patent number: 9998689
    Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 12, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics SA
    Inventors: David Coulon, Benoit Deschamps, Frederic Barbier
  • METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180158530
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Method for managing a fail bit line of a memory plane of a non volatile memory and corresponding memory device
    Patent number: 9984770
    Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 29, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Gineuve Alieri
  • Method for processing a signal coming from a transmission channel
    Patent number: 9985688
    Abstract: A method is for processing a channel analog signal coming from a transmission channel. The method may include converting the channel analog signal into a channel digital signal, and detecting a state of the transmission channel based on the channel digital signal to detect whether the transmission channel is, over an interval of time, one or more of linear and time invariant and linear and cyclostationary.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 29, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Demaj, Yoann Bouvet
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145039
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDITION OF ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145027
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145040
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Method and device for transmitting information over a communication channel with variable impedance
    Patent number: 9979418
    Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Mark Wallis
  • Method for writing in an EEPROM memory and corresponding device
    Patent number: 9978452
    Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 22, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES
    Publication number: 20180130881
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Zener diode having an adjustable breakdown voltage
    Patent number: 9954119
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • METHOD FOR MANAGING CONTACTLESS COMMUNICATIONS AND CONTRACTLESS CHARGING WITH A SYSTEM, AND CORRESPONDING SYSTEM
    Publication number: 20180109294
    Abstract: A system includes an antenna, and communications circuitry coupled to the antenna and configured for at least one of receiving and transmitting information via the antenna based on a contactless communications protocol. A charger is configured for contactless charging a power supply module via the antenna. A controller is configured for selectively operating the communications circuitry and the charger.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Rizzo, Anthony TORNAMBE
  • INTEGRATED CIRCUIT WITH DECOUPLING CAPACITOR IN A STRUCTURE OF THE TRIPLE WELL TYPE
    Publication number: 20180102377
    Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.
    Type: Application
    Filed: April 13, 2017
    Publication date: April 12, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • INTEGRATED CIRCUIT CHIP REINFORCED AGAINST FRONT SIDE DEPROCESSING ATTACKS
    Publication number: 20180102328
    Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
    Type: Application
    Filed: May 26, 2017
    Publication date: April 12, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sébastien Petitdidier, Mathieu Lisart
  • Method of connecting one or more contactless components to a single antenna, and corresponding system
    Patent number: 9941935
    Abstract: An electronic device includes an antenna, an irremovable component, a removable component, an impedance matching circuit, and a controller. The impedance matching circuit is arranged in a first configuration corresponding to the removable component connected to the irremovable component. The impedance matching circuit has a first capacitor, a second capacitor, and a third capacitor. The controller is configured to arrange the impedance matching circuit in a second configuration corresponding to the removable component being disconnected from the irremovable component.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Rizzo, Alexandre Tramoni
  • Method of fabricating a vertical MOS transistor
    Patent number: 9941390
    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Memory cell comprising non-self-aligned horizontal and vertical control gates
    Patent number: 9941369
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 10, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Julien Delalleau, Arnaud Regnier
  • Non-volatile memory with a variable polarity line decoder
    Patent number: 9941010
    Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Method for verifying the authenticity of a product
    Patent number: 9934509
    Abstract: In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then communicated back to host device when a decision on product authenticity is made.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: April 3, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Denis Farison, Fabrice Romain, Christophe Laurencin
  • Mechanism for verifying the authenticity of a product
    Patent number: 9934508
    Abstract: The authenticity of a product associated with a host device is verified through a process. The product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The process involves, in a first phase, the sending by the host device of a control signal for executing a function, with the product functioning to decipher the function and store the unciphered function in the non-volatile memory. The process further involves, in a second phase, the sending by the host device of a control signal for causing execution of the deciphered function, with the product functioning to execute the function and send a result of this execution back to the host device. The host device evaluates the received result to verify product authenticity.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: April 3, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Denis Farison, Fabrice Romain, Christophe Laurencin