Abstract: The present disclosure relates to a cryptographic method including the execution, by a cryptographic circuit, of an algorithm applied to a scalar in order to generate an output vector, of length L+n, which digits are d0, . . . , dL+n?1, the algorithm comprising iterations i, each iteration i taking an input data value, initially equal to said scalar and an input vector of length c, which digits are d?i, . . . , d?i+c?1, where for each j?{i, . . . , i+c?1}, the digit d?j is such that: d j ? = { d j ? if ? j < L d j - m ? otherwise .

Abstract: Provided is a voltage regulator supplying a first voltage on a first output node and comprising a first input transistor of a non-inverting stage and a second biasing transistor of the non-inverting stage. The first and second transistors are coupled in series, in this order, between the first node and a second node of application of a second reference voltage. The second transistor is being configured to be controlled by a third voltage depending on the first voltage.

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

Abstract: In an embodiment, an NFC controller of an NFC device is configured to transmit, after the detection, by the NFC controller, of an NFC reader in relation with a first NFC transaction and prior to receiving an application selection command from the NFC reader, an application selection message to a transaction handling element of the NFC device.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.

Abstract: A method can be used to process an initial set of data through a convolutional neural network that includes a convolution layer followed by a pooling layer. The initial set is stored in an initial memory along first and second orthogonal directions. The method includes performing a first filtering of the initial set of data by the convolution layer using a first sliding window along the first direction. Each slide of the first window produces a first set of data. The method also includes performing a second filtering of the first sets of data by the pooling layer using a second sliding window along the second direction.

Abstract: The present description concerns an electronic device comprising a semiconductor substrate, transistors having their gates contained in first trenches extending in the substrate, and at least one electronic component, different from a transistor, at least partly formed in a first semiconductor region contained in a second trench extending in the semiconductor substrate parallel to the first trenches.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

Abstract: The present disclosure relates to an electronic device comprising a semiconductor substrate and transistors having their gates contained in trenches extending in the semiconductor substrate, each transistor comprising a doped semiconductor well of a first conductivity type, the well being buried in the semiconductor substrate and in contact with two adjacent trenches among said trenches, a first doped semiconductor region of a second conductivity type, covering the well, in contact with the well, and in contact with the two adjacent trenches, a second doped semiconductor region of the second conductivity type more heavily doped than the first semiconductor region, extending in the first semiconductor region, and a third doped semiconductor region of the first conductivity type, more heavily doped than the well, covering the well, in contact with the first region, and extending in the semiconductor substrate in contact with the well.

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

Abstract: A device includes a memory, which, in operation, stores one or more look-up tables, and cryptographic circuitry coupled to the memory. The cryptographic circuitry, in operation, multiplies first data masked with a first mask by second data masked with a second mask, and protects the first data and the second data during the multiplying. The multiplying and protecting includes remasking the first data with a third mask, remasking the second data with a fourth mask, executing one or more compensation operations using one or more of the one or more look-up tables, and generating third data masked with a fifth mask. The fifth mask is independent of the first, second, third, and fourth masks. The third data corresponds to the first data multiplied by the second data.

Abstract: The present disclosure relates to a method of fault detection in an application, by an electronic circuit, of a first function to a message, including the steps of generating, from the message, a non-zero even number N of different first sets, each including P shares; applying, to the P shares of each first set, one or a plurality of second functions delivering, for each first set, a second set including Q images; and cumulating all the images, starting with at most Q-1 images selected from among the Q images of a same second set.

Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.