Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Detection of a NFC device
    Patent number: 10505592
    Abstract: A method of detection of the presence, by a first NFC device, of a second NFC device, during periodic field emission bursts, where detection thresholds are adjusted according to results obtained during one or a plurality of previous bursts.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Tramoni, Nicolas Cordier, Anthony Tornambe
  • METHOD FOR PRODUCING TRANSISTORS, IN PARTICULAR SELECTION TRANSISTORS FOR NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE
    Publication number: 20190371858
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Philippe BOIVIN, Jean-Jacques FAGOT
  • METHOD FOR GENERATING A BIAS CURRENT FOR BIASING A DIFFERENTIAL PAIR OF TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20190372537
    Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Vincent BINET, Yohan JOLY
  • Decoupling capacitor
    Patent number: 10497653
    Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 3, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Benoit Froment
  • Apparatus and process for controlling sense current in a non-volatile memory
    Patent number: 10497449
    Abstract: In an embodiment, a method is provided for controlling a level of a read current in a non-volatile memory that is powered by a supply voltage includes. A model current representative of an actual current able to flow during a readout through a read path of the memory is determined based on the value of the supply voltage. The model current is compared to a reference current having a reference value. A control signal is generated. The control signal is to control the generation of the read current having a level equal to the lowest value between a fraction of the value of the model current and the reference value.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 10490632
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • PROTECTION OF INTEGRATED CIRCUITS
    Publication number: 20190355674
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Denis FARISON, Romain COFFY, Jean-Michel RIVIERE
  • METHOD FOR MANAGING THE VALUE OF THE SUPPLY VOLTAGE FOR A MODULE OF AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT
    Publication number: 20190354728
    Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS, Yanis LINGE, Jimmy FORT
  • Resistive RAM memory cell
    Patent number: 10482957
    Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 19, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Simon Jeannot, Olivier Weber
  • Integrated circuit chip stack
    Patent number: 10473709
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Controllable integrated capacitive device
    Patent number: 10475713
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • INTEGRATED CIRCUIT COMPRISING A CAPACITIVE ELEMENT, AND MANUFACTURING METHOD
    Publication number: 20190341446
    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 7, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Frequency adjustment of an NFC circuit
    Patent number: 10454530
    Abstract: A near-field communication circuit includes an oscillating circuit having a controllable capacitor. A control circuit is coupled to the oscillating circuit to control the controllable capacitor. A battery is coupled to the control circuit to enable control when the near-field communication circuit is in a standby mode. The near-field communication circuit can be utilized by a mobile communication device.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Method for detecting thinning of an integrated circuit substrate via its rear face, and corresponding integrated circuit
    Patent number: 10453808
    Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Abderrezak Marzaki
  • Method for writing in an EEPROM memory and corresponding device
    Patent number: 10446235
    Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Circuit and method for activating an NFC device
    Patent number: 10447345
    Abstract: An embodiment near-field communication (NFC) router, includes a first switch coupled between a first terminal of the NFC router and a second terminal of the NFC router; and a rectifier bridge having an output terminal coupled to a control terminal of the first switch, the rectifier bridge being configured to rectify a signal detected by an antenna external to the NFC router.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nathalie Vallespin
  • Random number generator
    Patent number: 10445068
    Abstract: An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Patrick Haddad, Viktor Fischer
  • Protection of a security element coupled to an NFC circuit
    Patent number: 10440575
    Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: October 8, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Charles
  • Compact non-volatile memory device of the type with charge trapping in a dielectric interface
    Patent number: 10438960
    Abstract: Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Contactless communication and contactless charging in a system
    Patent number: 10432268
    Abstract: A system includes an antenna, and communications circuitry coupled to the antenna and configured for at least one of receiving and transmitting information via the antenna based on a contactless communications protocol. A charger is configured for contactless charging a power supply module via the antenna. A controller is configured for selectively operating the communications circuitry and the charger.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Rizzo, Anthony Tornambe