Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Method and device for controlling operation of the power supply of a processing unit by making a periodic voltage comparison
    Patent number: 10303234
    Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Bruno Gailhard
  • Semiconductor structure and memory device including the structure
    Patent number: 10304524
    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 28, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Connecting bar
    Patent number: 10304775
    Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Delia Ristoiu
  • Switch-mode power supply control
    Patent number: 10298109
    Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean-Francois Link, Vincent Onde
  • Method for detecting the eventual presence of an object by a contactless reader, and corresponding reader
    Patent number: 10298295
    Abstract: A method can be used for detecting a potential presence of an object by a reader capable of mutually communicating via a contactless communications protocol. An antenna of the reader transmits a magnetic field on a carrier signal having a sub-carrier modulated by a first data sequence. The modulated sub-carrier is non-interpretable by the object. The antenna of the reader receives a signal resulting from the transmission. The reader demodulates the sub-carrier of the resulting signal so as to extract a second data sequence from the resulting signal. The first data sequence and second data sequence are correlated and the potential presence or absence of the object is determined based upon the result of the correlating.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • CHIP CONTAINING AN ONBOARD NON-VOLATILE MEMORY COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20190140176
    Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
  • DEVICE FOR DETERMINING THE MOVEMENT OF A ROTARY ELEMENT, PARTICULARLY FOR READINGS OF WATER AND/OR GAS METERS
    Publication number: 20190137302
    Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 9, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Vincent ONDE
  • Resistive memory cell having a compact structure
    Patent number: 10283563
    Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 7, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Simon Jeannot
  • PN junction-based electrical fuse using reverse-bias breakdown to induce an open conduction state
    Patent number: 10283648
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronic (Rousset) SAS
    Inventor: Pascal Fornara
  • Testing circuit of a longtime-constant circuit stage and corresponding testing method
    Patent number: 10281512
    Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 7, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
    Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
  • Non-volatile memory device having a memory size
    Patent number: 10275173
    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 30, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • ELECTRONIC CIRCUIT WITH DEVICE FOR MONITORING A POWER SUPPLY USING A TRIP THRESHOLD CHOSEN FROM A RANGE OF VOLTAGES AROUND A BAND GAP VOLTAGE
    Publication number: 20190123737
    Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy FORT, Nicolas BORREL, Francesco LA ROSA
  • ELECTRONIC CIRCUIT WITH DEVICE FOR MONITORING A POWER SUPPLY
    Publication number: 20190123736
    Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas BORREL, Jimmy FORT, Francesco LA ROSA
  • Method and device for managing information exchange between a main element, for example a NFC controller, and a set of at least two auxillary elements
    Patent number: 10271193
    Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 23, 2019
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS GMBH
    Inventors: Thierry Meziache, Pierre Rizzo, Alexandre Charles, Juergen Boehler
  • DEVICE AND METHOD FOR SWITCHING AN ELECTRICAL SYSTEM INTO STANDBY MODE
    Publication number: 20190113897
    Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Method of processing digital signals, in particular digital acoustic signals, by sample skipping and decimation filtering and corresponding device
    Patent number: 10264353
    Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SAS
    Inventors: Jean Claude Bini, Dragos Davidescu, Igor Cesko, Jonathan Cottinet
  • Protection of a calculation against side-channel attacks
    Patent number: 10263768
    Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Method for wear leveling in a nonvolatile memory
    Patent number: 10261702
    Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • METHOD FOR DETECTING A DIFFERENTIAL FAULT ANALYSIS ATTACK AND A THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT
    Publication number: 20190109100
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 11, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • DETECTION OF A TIME CONDITION RELATIVE TO A TWO-WIRE BUS
    Publication number: 20190102328
    Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois TAILLIET