Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract: A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.

Abstract: A method of reading voltages from an image sensor having an array of pixels, each pixel Having at least one photodiode connectable to a storage node, the method including: controlling each pixel in a row of pixels to store and output a first voltage value at a first instance, a second voltage value at a second instance, and a third voltage value at a third instance, the first, second and third voltage values being representative of charge accumulated by the photodiodes during an integration phase; comparing the first voltage value from each pixel with a reference threshold; sampling for each pixel, based on the comparison, one of the second and third voltage values: and generating an output pixel value based on the sampled one of the second and third voltage values

Abstract: The invention concerns an inductive element for forming an electromagnetic transponder antenna, comprising a first group of mutually parallel conductors coplanar in a first plane, a second group of mutually parallel conductors coplanar in a second plane parallel to the first plane, and an insulating material separating the two groups of conductors, one end of each conductor of the first group being connected to one end of a conductor of the second group whereof the other end is connected to one end of another conductor of the first group, the connections between the conductors being conductive via holes in the thickness of the insulating material.

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Abstract: A semiconductor device includes several assembled integrated-circuit chips. A main integrated-circuit chip has at least one cavity in which electrical contacts are provided. A secondary integrated-circuit chip includes an edge which engages in the cavity of the main chip and has electrical contacts. When the secondary integrated-circuit chip is inserted into the cavity, the electrical contacts of the main chip and the electrical contacts of the secondary chip are placed so as to be in contact with one another.

Abstract: A thin soft magnetic film combines a high magnetization with an insulating character. The film is formed by nitriding Fe-rich ferromagnetic nanograins immersed in an amorphous substrate. A selective oxidation of the amorphous substrate is then performed. The result is a thin, insulating, soft magnetic film of high magnetization. Many types of integrated circuits can be made which include a component using a membrane incorporating the above-mentioned thin film.

Abstract: A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel.

Abstract: A transconducting device includes at least one transistor having a control electrode for receiving an input signal whose frequency spectrum contains two different frequencies, an output electrode for delivering an output signal, and a third electrode. The transconducting device further includes a voltage source for delivering a DC reference voltage, and a feedback controller for feedback-controlling the voltage on the third electrode to the DC reference voltage using a negative feedback loop. The negative feedback loop includes resistive damping, connects the third electrode and the control electrode, and has an open-loop gain greater than unity at a frequency equal to the frequency separation between the two different frequencies.

Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract: A method of reading voltages from an image sensor having an array of pixels, each pixel having at least one photodiode connectable to a storage node, the method having: controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode above a first threshold to the storage node at the start and end of a first integration period and reading a first voltage at the storage node of each pixel in the row at the end of the first integration period; controlling of the pixels in the row to transfer charge accumulated in the photodiode above a second threshold to the storage node at the start and end of a second integration period longer than the first integration period, and reading a second voltage value at the storage node of each pixel in the row at the end of the second integration period; controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode to the storage node at the end of a third integration period longer than the first and second integration perio

Abstract: A digital frequency synthesizer receiving a first signal corresponding to a periodic sequence of first pulses at a first frequency and providing a second signal corresponding to a periodic sequence of second pulses at a second frequency. The synthesizer includes a first circuit clocked by a third signal corresponding to a sequence of third pulses and obtained from the first signal, the first circuit providing a fourth digital signal which, for any set of third successive pulses, increases (decreases) on each pulse and decreases (increases) at the end of said set; and a second circuit receiving the first and fourth signals and providing, for each first pulse from among some at least of the first pulses, a second pulse which is shifted with respect to the first pulse by a duration which depends on the fourth signal.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).

Abstract: A method for controlling the execution of a program including of associating with each operator an initial digital code and a final digital code which are linked to each other by a degradation function applied a number of times depending on the execution of this operator; applying, to the content of a register initialized at each instruction beginning by the initial code of the corresponding operator, said degradation function a number of times depending on the operator execution; and checking, at least at each instruction end, the coherence between the register content and the final code of the corresponding operator.

Abstract: The invention concerns a method for transmitting digital messages through output terminals (22) of a monitoring circuit (18) integrated to a microprocessor (12), said messages representing specific events occurring upon the execution of instructions by the microprocessor comprising the step which consists, after or before transmitting at least one specific message associated with a particular event in transmitting a correlation message including an identifier of said specific message and a counter for the number of instructions executed by the microprocessor between the instruction associated with the transmission of said specific message and the instruction associated with a selected previous message. The invention also concerns a device for transmitting digital messages.

Abstract: A circuit of generation of a reference voltage by a first MOS transistor connected to a first terminal of application of a supply voltage, the first transistor being in series with a second MOS transistor controlled by an input stage of a transconductance amplifier and their junction point defining an output terminal providing the reference voltage, a first current source connecting the first supply terminal to a gate of the first transistor, a second current source connecting the second transistor to a second terminal of application of the supply voltage, at least one third MOS transistor connecting the two current sources, and a capacitive element directly connecting the output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in case of a variation in output voltage.

Abstract: A band pass filtering circuit based on a quadripole includes a serial branch having a first acoustic resonator presenting a frequency of resonance and a frequency of anti-resonance and mounted in serial with a first capacitor; a parallel branch having a second acoustic resonator resulting from the same manufacturing process as the first resonator and mounted in parallel with a second capacitor of identical value to that the first capacitor. The filtering circuit is particularly but not exclusively adapted to the realization of integrated filtering circuits used in mobile telephony.