Patents Assigned to STMicroelectronics S.A.
-
Publication number: 20220028769Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: STMicroelectronics S.r.l.Inventor: Federico Giovanni ZIGLIOLI
-
Publication number: 20220028979Abstract: An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.Type: ApplicationFiled: July 14, 2021Publication date: January 27, 2022Applicant: STMicroelectronics S.r.l.Inventors: Simone RASCUNA, Claudio CHIBBARO
-
Publication number: 20220027715Abstract: A method, comprising: providing an ANN processing stage having a plurality of processing layers with respective parameters including at least one set of weight parameters, at least one input, resp. output, activation parameter and at least one activation function parameter; setting to an integer value a dimensional parameter of a lattice having a plurality of lattice points and identified by a set of basis vectors; selecting a set of weight parameters of a respective processing layer; vectorizing the selected set of weight parameters producing a set of weight vectors arranged as items of a matrix of weight vectors; normalizing the matrix of weight vectors; applying lattice vector quantization, LVQ, processing to the matrix of normalized weight vectors, producing a codebook of codewords; indexing by encoding codewords of the codebook as a function of the lattice, producing respective tuples of indices.Type: ApplicationFiled: July 22, 2021Publication date: January 27, 2022Applicant: STMICROELECTRONICS S.r.l.Inventors: Diego CARRERA, Matteo COLELLA, Giuseppe DESOLI, Giacomo BORACCHI, Beatrice ROSSI, Pasqualina FRAGNETO, Luca FRITTOLI
-
Publication number: 20220026466Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: STMicroelectronics S.r.l.Inventor: Alberto Pagani
-
Patent number: 11229404Abstract: Blood pressure signals are reconstructed from PhotoPlethysmoGraphy (PPG) signals by: receiving PPG signals including systolic, diastolic and dicrotic phases; and determining first and second derivatives of the PPG signals and: a first set of values indicative of lengths of the signal paths of the PPG signal, the first derivative and the second derivative thereof in the systolic, diastolic and dicrotic phases; a second set of values indicative of relative durations of the PPG signal and the first and second derivatives thereof in the systolic, diastolic and dicrotic phases; and a third set of values indicative of the time separation of peaks and/or valleys in subsequent waveforms of the PPG signal. Reconstruction also includes applying artificial neural network processing to the first, second and third set of values. The artificial neural network processing includes artificial neural network training as a function of blood pressure signals to produce reconstructed blood pressure signals.Type: GrantFiled: November 19, 2018Date of Patent: January 25, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Francesco Rundo, Sabrina Conoci, Piero Fallica, Rosalba Parenti, Vincenzo Perciavalle
-
Patent number: 11233540Abstract: An embodiment method implemented by an agent device comprises receiving, by the agent device, from a device, a bootstrap request message over a first communication channel; transmitting, by the agent device, to a coordinating device, a request message comprising the bootstrap request message and a first channel type indicator indicating a channel type of the first communication channel; receiving, by the agent device, from the coordinating device, a response message comprising a bootstrap response message and a second channel type indicator indicating the channel type of the first communication channel; and transmitting, by the agent device, to a device, the bootstrap response message over a second communication channel in accordance with the second channel type indicator.Type: GrantFiled: March 23, 2021Date of Patent: January 25, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Matteo Varesio, Paolo Treffiletti
-
Publication number: 20220020884Abstract: The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.Type: ApplicationFiled: July 8, 2021Publication date: January 20, 2022Applicant: STMICROELECTRONICS S.R.L.Inventor: Simone RASCUNÁ
-
Patent number: 11227086Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.Type: GrantFiled: May 13, 2020Date of Patent: January 18, 2022Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Thomas Boesch, Giuseppe Desoli
-
Patent number: 11227992Abstract: A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.Type: GrantFiled: May 26, 2020Date of Patent: January 18, 2022Assignee: STMicroelectronics S.r.l.Inventor: Paolo Giuseppe Cappelletti
-
Publication number: 20220012569Abstract: A computer-implemented method applies a pooling operator to an input array of data, the pooling operator having an absorbing element value and a set of pooling parameters. A size of an output buffer is computer as a function of the set of pooling parameters. The elements of the output buffer are initialized to the value of the absorbing element of the pooling operator. The output array of data is generated by, for a plurality of iterations associated with respective pooling windows: associating, as a function of the pooling parameters, elements of the input array of a pooling window with output elements of the output buffer; and combining, for each output element of the output buffer, the respective input elements associated with the output element. The combining may include determining a combination of respective elements of the output buffer with the input elements associated with the output elements.Type: ApplicationFiled: July 7, 2021Publication date: January 13, 2022Applicant: STMICROELECTRONICS S.r.l.Inventor: Emanuele PLEBANI
-
Publication number: 20220011567Abstract: A MEMS micromirror device is formed in a package including a containment body and a lid transparent to a light radiation. The package forms a cavity housing a tiltable platform having a reflecting surface. A metastructure is formed on the lid and/or on the reflecting surface and includes a plurality of diffractive optical elements.Type: ApplicationFiled: July 7, 2021Publication date: January 13, 2022Applicant: STMicroelectronics S.r.l.Inventors: Roberto CARMINATI, Nicolo' BONI, Massimiliano MERLI, Enri DUQI
-
Publication number: 20220013982Abstract: An electronic device is couplable to a plurality of laser diodes and includes a control switch having a drain coupled to a drain metallization and having a source coupled to a first source metallization that is electrically couplable to cathodes of the laser diodes. Each of a plurality of first switches has a drain coupled to the drain metallization and a source coupled to a respective second source metallization that is couplable to an anode of the laser diodes. The second source metallizations are aligned with one another in a direction of alignment, overlie, in a direction orthogonal to the direction of alignment, the respective sources of the first switches, and can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diodes. At least one of the sources of the first switches can be aligned, in a direction orthogonal to the direction of alignment, to the respective laser diode.Type: ApplicationFiled: July 6, 2021Publication date: January 13, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SASInventors: Antonio Filippo Massimo PIZZARDI, Santo Alessandro SMERZI, Ferdinando IUCOLANO, Romeo LETOR
-
Publication number: 20220013439Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.Type: ApplicationFiled: July 2, 2021Publication date: January 13, 2022Applicant: STMicroelectronics S.r.l.Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
-
Patent number: 11223279Abstract: An electronic converter comprises first and second electronic switches that are connected between positive input and output terminals, where an intermediate node between the first and second electronic switches represents a first switching node. Third and fourth electronic switches are connected between the positive output terminal and a negative input terminal, where an intermediate node between the third and fourth electronic switches represents a second switching node. A first terminal of a primary winding of a transformer is connected to the second switching node, and a capacitor and inductance are connected in series between a second terminal of the primary winding and the first switching node. Fifth and sixth electronic switches are connected between the positive output terminal and a negative output terminal, where a first terminal of the secondary winding is connected to an intermediate node between the fifth and sixth electronic switches.Type: GrantFiled: May 5, 2020Date of Patent: January 11, 2022Assignee: STMICROELECTRONICS S.R.L.Inventor: Osvaldo Enrico Zambetti
-
Patent number: 11222969Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.Type: GrantFiled: March 3, 2020Date of Patent: January 11, 2022Assignee: STMicroelectronics S.r.l.Inventors: Ferdinando Iucolano, Alfonso Patti
-
Publication number: 20220005702Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.Type: ApplicationFiled: July 6, 2021Publication date: January 6, 2022Applicant: STMicroelectronics S.r.l.Inventors: Nicolo' PILUSO, Andrea SEVERINO, Stefania RINALDI Beatrice, AngeloAnnibale MAZZEO, Leonardo CAUDO, Alfio RUSSO, Giovanni FRANCO, Anna BASSI
-
Publication number: 20220006988Abstract: A light projection system includes a MEMS mirror operating on a mirror drive signal to generate a mirror sense signal resulting from operation of the MEMS mirror based on the mirror drive signal. A mirror driver generates the mirror drive signal from a drive control signal. A controller receives the mirror sense signal from the MEMS mirror, obtains a first sample of the mirror sense signal at a first phase thereof, obtains a second sample of the mirror sense signal at a second phase thereof, wherein the first and second phases are separated by a half period of the mirror drive signal, with the second phase occurring after the first phase, and generates the drive control signal based on a difference between the first and second samples to keep the mirror drive signal separated in phase from the mirror sense signal by a desired amount of phase separation.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicants: STMicroelectronics LTD, STMicroelectronics S.r.l.Inventors: Massimo RATTI, Eli YASER, Naomi PETRUSHEVSKY, Yotam NACHMIAS
-
Patent number: 11214061Abstract: The microfluidic device has a plurality of ejector elements. Each ejector element includes a first region, accommodating a first fluid flow channel and an actuator chamber; a second region, accommodating a fluid containment chamber; and a third region, accommodating a second fluid flow channel. The fluid containment chamber is fluidically coupled to the first and to the second fluid flow channels. The second region is formed from a membrane layer, from a membrane definition layer, mechanically coupled to the membrane layer and having a membrane definition opening, and a fluid chamber defining body, mechanically coupled to the membrane definition layer and having a chamber defining opening, with a width greater than the width of the membrane definition opening. The width of the membrane is thus defined by the width of the chamber defining opening.Type: GrantFiled: May 28, 2020Date of Patent: January 4, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Domenico Giusti, Mauro Cattaneo, Carlo Luigi Prelini
-
Publication number: 20210405346Abstract: A MEMS actuator includes a main body having a central portion, couplable to a substrate, and a peripheral portion suspended over the substrate when the central portion is coupled to the substrate. The peripheral portion has a deformable structure extending around the central portion, and forming successively arranged membranes. The MEMS actuator includes bearing structures and corresponding piezoelectric actuators. The bearing structures are fixed at their top to the deformable structure and laterally delimit corresponding cavities, each having a lateral opening facing the central portion of the main body and closed at the top by a membrane. A fixed part of the membrane is fixed to the underlying bearing structure and a suspended part is laterally offset with respect to the underlying bearing structure. The piezoelectric actuators are controllable to cause deformation of the corresponding membrane and rotation of the bearing structures around the central portion of the main body.Type: ApplicationFiled: June 23, 2021Publication date: December 30, 2021Applicant: STMicroelectronics S.r.l.Inventors: Domenico GIUSTI, Massimiliano MERLI
-
Publication number: 20210402559Abstract: A method for evaluating the physical consumption of a polishing pad of a CMP apparatus provided with an eddy current sensor that is configured to sense a distance with a substrate on which a layer to be processed extends. The method includes: generating a magnetic field adapted to induce eddy currents in the layer; acquiring an eddy current signal generated by the layer in response to the magnetic field; calculating an average value of the eddy current signal in the initial time frame; comparing the average value with a pre-set threshold value; and determining a maintenance condition of the polishing pad based on a result of the comparison.Type: ApplicationFiled: June 29, 2021Publication date: December 30, 2021Applicant: STMicroelectronics S.r.l.Inventors: Renato CORETTI, Simone RIZZARDINI, Valentina ROBBIANO