Abstract: A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be support and hides memory access latency.

Abstract: A non-volatile memory device is provided that can be irreversibly programmed electrically. The device includes a memory plane formed from a matrix of memory cells, with each of the memory cells including an access transistor and a capacitor. The memory cell matrix includes first groups of memory cells laid out in a first direction and second groups of memory cells laid out in a second direction. Each first group includes memory cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes memory cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together.

Abstract: A method for forming a capacitor with metal armatures in metallization levels above an integrated circuit, including the steps of: depositing over the surface of an integrated circuit an insulating layer having a thickness ranging between 0.5 and 1.5 &mgr;m; digging into the insulating layer to form trenches, of which at least a portion in top view is parallel and separate from one trench to the other; depositing and leveling a metallic material to form conductive lines in the trenches; locally removing the insulating layer to remove it at least from all the intervals separating two conductive lines; conformally depositing a dielectric; and depositing and etching a second metallic material to at least completely fill the intervals between lines.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: The beam reflected by the mobile carrier is picked up by an optical pickup having several photodetectors. The elementary signals respectively delivered by the photodetectors are used to formulate two secondary signals, sampled and filtered by a low-pass filter having a cutoff frequency at most equal to a quarter of the sampling frequency. The mutual phase shift of the two secondary signals is representative of the positioning error TE of the beam with respect to the track. The determination of a value of the mutual phase shift comprises the selecting, for each secondary signal, of at least one pair of samples situated outside a predetermined amplitude range around a predetermined threshold. This makes it possible to tag, respectively for the two secondary signals, two transitions of these secondary signals with respect to the threshold and corresponding to one and the same direction of crossing of the threshold.

Abstract: Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.

Abstract: A method and a system of data transmission between a terminal for generating an electromagnetic field and a transponder, the terminal and the transponder each including an oscillating circuit forming an antenna, and the transponder including an electronic circuit adapted to absorbing and giving back power provided by the terminal field, the oscillating circuits of the transponder and of the terminal being capable of transmitting radio-electric signals of determined frequency, this method including causing a detuning of at least one of the oscillating circuits with respect to the determined frequency when the transponder and the terminal are very close to each other.

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract: A low-pass filter with a variable gain comprising a transconductance differential amplifier stage comprising a differential input and a differential output, the latter receiving a passive circuit, such as a first-order RC filter, in order to realize low-pass filtering of the amplifier stage. The filter is chosen so that the cut-off frequency is below the frequency range to be treated. The filter further comprises a control element controlling the differential amplifier stage's bias point to allow control of the gain associated to filtering. Thus, low-pass filtering associated to a variable gain can be realized in a very simple way. The circuit is perfectly adapted for incorporation into a semiconductor product.

Abstract: A sinusoidal frequency generator comprising an oscillation circuit controlled by a control voltage, characterized in that the oscillating circuit is a gyrator made up of two transconductance amplifiers whose bias points are fixed by the control voltage in order to regulate oscillation frequency. The gyrator is easy to integrated in a phase control loop in order to realize a square-to-sinusoidal frequency converter.

Abstract: A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.

Abstract: A modulation process for a digital transmission system having an error correcting code and determination of the number of bits to load on a transmission channel. The process judiciously associates a coder for introducing redundancy to the binary information, an interleaver for suppression the correlation to the encoded information and a labeling of the same based on a GRAY type coding in order to associate the said binary information with points of a constellation which is selected among a predetermined set of constellations. The process achieves a precise determination of the order and size of the constellation to utilize and, therefore, the computation of the bit loading as a function of the signal to noise ratio measured in reception and as a function of the bit error rate Pbit at the output of the receiver. The process is well adapted to the Multi Tone transmission system, and to the use of turbo codes.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit using a filtering time delay in generating a detection signal with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time delay is controlled with the power transistor switching time.

Abstract: An injection mold is provided for injection molding an encapsulation material to encapsulate at least one integrated circuit chip. The injection mold includes at least two parts that define at least one injection circuit, and at least one blind complementary channel communicating with the injection circuit. The injection circuit includes at least one injection cavity for housing the chip, at least one transfer chamber from which the encapsulation material is injected, and at least one injection channel connecting the transfer chamber to the injection cavity. The blind complementary channel is formed between the two parts of the mold and forms at least one appendage of encapsulation material that is connected to the encapsulation material that fills the injection circuit. Also provided is a method for injection molding an encapsulation material to encapsulate at least one integrated circuit chip.

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints.

Abstract: A control device is provided for a switching power supply having an output that supplies an output voltage. The switching power supply includes an inductor and two changeover switches for controlling coupling of the inductor. The control device includes a first capacitor for charging with continuous current from a 0 V voltage level, a second capacitor for discharging of the continuous current from a predetermined voltage level that is greater than the voltage level of a DC power supply, and a comparison circuit. The comparison circuit compares the output voltage of the switching power supply with voltage levels of the first and second capacitors and generates control signals for controlling the two changeover switches of the switching power supply. Also provided are switching power supplies having such control devices and a method for controlling a switching power supply.

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract: A line scan circuit for a CRT, including, in series across a switch, two oscillating circuits having the same time constant, each including, in parallel, a capacitor, a diode connected in antiparallel, and a series association of an inductor and of a voltage source, the inductor of a first one of the oscillating circuits being a scan coil of the CRT; an amplifier receiving a set-point voltage and using, as a feedback, a voltage taken from one of the oscillating circuits, and providing an adjustable voltage source to the second oscillating circuit.

Abstract: A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal defects resulting from the implantation; depositing an epitaxial layer; digging trenches delimiting each implanted region; and annealing the buried layers, the lateral diffusion of which is blocked by said trenches, said trenches being deeper than the downward extension of the diffusions resulting from said implantations.

Abstract: A linear interpolation operator for determining the value y of a function of x when one knows the value y1 corresponding to x1, and a value y2 corresponding to x2 (where x2<x≧x1), comprises a first calculation circuit which determines the equation (xm+xM)/2; a second calculation which determines the equation (ym+yM)/2; a comparison circuit which compares x with (xm+xM)/2 so as to determine which one of the intervals [xm,(xm+xM)2], [(xm+xM)/2, xM] contains x and to feed back the limits of the selected interval into the first calculation circuit and the limits of the interval corresponding in y into the second calculation circuit.