Abstract: A generator of at least one pulse width modulated signal, including: a generator of a sawtooth signal a generator of high and low reference signals defining, based on a set-point signal, a linear range of each ramp of the sawtooth signal at least one element of comparison of the sawtooth signal with each of the reference signals and at least one element of logic combination of the comparison results, providing the pulse width modulated signal.

Abstract: A control procedure is provided for use during a regulation stage and according to a set point of a physical dynamic system, the set point being subject to, whilst operating, the influence of several physical quantities represented by input parameters, and adopting a behavior defined by at least a first physical output parameter, obliged to take a value represented by the set point, the first output parameter being linked to at least a first of the input parameters by a first transfer function of the system. According to the control procedure, a characterization stage is implemented in which at least a first inverse transfer function linking the first input parameter to the first output parameter is experimentally determined. A modeling stage is implemented in which the first inverse transfer function is translated through a fuzzy logic model in the form of a first set of ranges of the first output parameter, to each of which is attributed a specific value of the first input parameter.

Abstract: A system and method are provided for displaying a video composed of images each comprising a predetermined number M of lines and, a predetermined number N of pixels in each line. Values of a predetermined number P of reference pixels for each line of a current image of the video are stored in memory, where P is less than N. For each line of the current image, the value of a parameter associated with the line is determined, with the parameter corresponding to the number of the reference pixels of the line that are black according to a first predetermined criterion. A first nonblack line and a last nonblack line of the current image are determined to serve as a basis for an automatic reframing of the images of the video before display.

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

Abstract: A routing device is provided for transporting digital data from demodulated digital television signals. The routing device includes a network that routes the digital data to demultiplexers via at least one decoding module. The network includes means for connecting to at least two independent demodulation channels, with each of the demodulation channels producing digital data from a demodulator. The network allows individual routing of the digital data from each of the demodulation channels to the demultiplexers via at least one decoding module. Also provided are a corresponding routing method and a host device that includes such a routing device. Exemplary applications of the routing device and method are a digital television receiver with an image incorporation (picture in picture) function, and a digital television combined with a recording device.

Abstract: Interleaved type processing includes a preprocessing phase in which for each initial symbol received an auxiliary symbol that includes N auxiliary complex samples is formulated, and a processing phase that includes for each auxiliary symbol an inverse Fourier transform calculation of size N. The processing phase includes elementary processing of the butterfly type corresponding to several stages of a general butterfly-like calculation graph. The various stages of the graph are implemented within a pipelined architecture. Upon receiving an initial symbol, two separate random access memories are simultaneously used to respectively store in a first memory the auxiliary symbol corresponding to this initial symbol, and to perform on the basis of the content of the second memory the elementary processing corresponding to a first stage of the graph. The two memories are swapped with each new receipt of an initial symbol.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A controllable rectifying element, comprising a bipolar transistor having a current input terminal connected to a control terminal by a first switch and having a current output terminal connected to the control terminal by a second switch, the turn-off and turn-on phases of the first and second switches being complementary and depending on the state desired for the rectifying element.

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Abstract: A generator of random numbers by a flip-flop having a data input receiving a first signal at a first frequency comprised in a predetermined range and the instantaneous value of which is conditioned by a disturbing signal, and having a clock input receiving a second signal at a second predetermined frequency, smaller than the first one, said second signal passing through a delay element giving it a delay greater than or equal to the maximum period of the first signal.

Abstract: An electromagnetic transponder intended to draw the power necessary to its operation of from a field radiated by a terminal of transmission of a carrier at a first supply frequency and to back-modulate the received signal at the rate of a sub-carrier at a second frequency lower than the first one, and comprising means capable of demodulating and decoding signals modulated by said sub-carrier, as well as a system of communication between such transponders.

Abstract: A digital image processing circuit for replacing an input code associated with a pixel of the image with an output code selected in a first memory containing a set of codes, including an input bus for receiving the input code, an output bus for providing the output code, said first memory, means of address calculation of the first memory, means of address selection of the first memory between the input code and an address code generated by the address calculation means, a second memory for containing an address code generated by the address calculation means, and means of selection of the output code between a code read from the first memory and said code contained in the second memory.

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: A method and a system determine a score characteristic of the definition of a digital imageby cumulating the quadratic norm of horizontal and vertical gradients of luminance values of pixels of the image, the pixels being chosen at least according to a first maximum luminance threshold of other pixels in the concerned direction.

Abstract: A MOS power transistor formed in an epitaxial layer of a first conductivity type, the MOS power transistor being formed on the front surface of a heavily-doped substrate of the first conductivity type, including a plurality of alternate drain and source fingers of the second conductivity type separated by a channel, conductive fingers covering each of the source fingers and of the drain fingers, a second metal level connecting all the drain metal fingers and substantially covering the entire source-drain structure. Each source finger includes a heavily-doped area of the first conductivity type in contact with the epitaxial layer and with the corresponding source finger, and the rear surface of the substrate is coated with a source metallization.

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract: A circuit including a memory connected to be accessible from a bidirectional bus, an MPEG decoder connected to the bus to be able to read coded and decoded data in the memory, and having a decoded data output connected to the bus according to a first path to be able to read from the memory data of a first image, and a first image display circuit, an input of which is connected to the bus to read from the memory the data written by the decoder, which also includes a decimator circuit, connected between the output of the decoder and the bus according to a second path to be able to write into the memory data of a second image, and a second image display circuit connected to the bus to read from the memory the data written by the decimator circuit.

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.