Abstract: The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

Abstract: A cathode-ray tube video device connected to a power source and having a first normal operating state and at least a second operating state at reduced power (stand-by mode) includes a switching power supply and a circuit portion for demagnetizing the cathode-ray tube coupled to the power source through an electrically actuated switch. The switch is closed to demagnetize the cathode-ray tube during the first operating state of the device, and opened during the second operating state at reduced power of the device.

Abstract: A DC/DC conversion circuit, adapted to convert a DC input voltage to a DC output voltage, employs a PNP type of bipolar power transistor as a synchronous rectifier element, to allow power-on through a simplified control circuitry capable of sensing, automatically and at a high speed, the difference of potential across the switch. This approach allows power to be transferred from the input to the output unilaterally, while automatically controlling the depth of saturation of the power transistor and regulating its base current.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: A multiple-level memory cell is capable of taking on a plurality of states, with each state being represented by a different value of a physical quantity and being associated with a corresponding logic value. A method for reading the memory cell includes the step of setting an actual physical quantity to a value correlated with the value of the physical quantity corresponding to the state of the memory cell. This step is repeated until the logic value corresponding to the state of the memory cell is determined. A cycle includes the step of setting a component of the logic value to a value which is a function of a range in which the actual physical quantity lies, as determined by comparing the actual physical quantity with at least one reference physical quantity having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity.

Abstract: A device for analog programming is disclosed. The device comprises a current mirror circuit connected to drain terminals of a cell to be programmed and of a MOS reference transistor. An operational amplifier has inputs connected to the drain terminals of the cell and respectively of the MOS transistor and an output connected to the control terminal of the MOS transistor. During programming, the control and drain terminals of the cell are biased at corresponding programming voltages and the output voltage of the operational amplifier, which is correlated to the current threshold voltage level of the cell, is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.

Abstract: A control circuit comprises a plurality of input terminals and an output terminal for biasing a floating well in a semiconductor integrated circuit structure. The control circuit also includes a first transistor which has its conduction terminals connected between a first input terminal and an output terminal, and a second transistor which has its conduction terminals connected between a second input terminal and the output terminal. The control circuit further includes a regulator coupling the output terminal to each of the control terminals of said first and second transistors.

Abstract: An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element connected between a voltage reference and the cell matrix to enable the program mode of the cell matrix under control by the microcontroller.

Abstract: The invention relates to a circuit architecture for easily carrying out tests on a non-volatile memory device having at least one matrix (2) of memory cells. The architecture is distinctive in that it comprises a bi-directional internal data bus (3) extending from one end to the other of the memory device, a plurality of signal sources (8) inside said memory device, at least one local bus (6) connected to the data bus (3), and timing means (10) for timing the access of the local bus (6) to the data bus (3) and the selective access of the signal sources (8) to the local bus (6) during the same test cycle.

Abstract: A flyback DC--DC converter employs a flyback transformer for storing and transferring energy to a load having an auxiliary winding whose voltage is compared by a comparator with a threshold to detect its crossing. As a consequence, a power transistor driving the primary winding of the transformer is switched on through a control flip-flop, for a new phase of conduction and accumulation of energy, whose duration is established by a secondary control loop of the output voltage producing the switching off of the power transistor for a successive energy transfer phase toward the load of the energy stored in the transformer during the preceding conduction phase. The converter has a wholly integrated control circuit that includes a second comparator of the voltage existing on the current terminal of the power transistor connected to the primary winding of the transformer with respect to the ground potential of the circuit.

Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.

Abstract: A current mirror circuit is provided with recovery having high output impedance. The current mirror includes a differential stage having a pair of transistors, and a voltage feedback loop which is stabilized and closed on a first one of the transistors of the differential stage. A second one of the transistors of the differential stage is connected, by its base terminal, to the collector terminal of an output transistor and, by its collector terminal, to the supply voltage. Moreover, the circuit includes a positive feedback loop which has the second transistor of the differential stage and the output transistor. A low-impedance circuit branch is connected to the base terminal of the second transistor of the differential stage and to the collector terminal of the output transistor.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.

Abstract: The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

Abstract: A current sensing circuit with high input impedance comprises a first transconductance amplifier connected across the terminals of a resistor, through which a current to be measured flows. A voltage amplifier is cascade-connected to the first transconductance amplifier. A second transconductance amplifier is feedback connected between an output of the voltage amplifier and a virtual ground node of the voltage amplifier. A ratio between the output voltage of the voltage amplifier and the voltage across the resistor are equal, in absolute value, to a ratio of the transconductances of the first and second transconductance amplifiers.

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an array of memory cells formed within said second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in said second well, and a control gate electrode.

Abstract: A protection circuit for a power supply line in a semiconductor device, comprising first and second field-effect transistors, both transistors having their respective drain terminals connected to the power supply line. The gate source terminals of the first transistor are connected to ground through first and second resistors, respectively. The gate and source terminals of the second transistor are connected to the source terminal of the first transistor and to ground, respectively.

Abstract: The invention relates to a dynamic sense amplifier, particularly for semiconductor memory devices of the EPROM, EEPROM and Flash-EPROM types, which includes a virtual ground sense circuit having a pair of output nodes, an equilibration device for equalizing the voltages at the output nodes, and respective reference and matrix circuit legs associated with the output nodes and being led to respective input terminals, the sense amplifier also includes a bias circuit portion for biasing the input terminals. The inventive amplifier distinguishes itself in that the sense circuit and equilibration device are driven by respective signals to generate a predetermined differential voltage between the output nodes before the sense circuit is activated.

Abstract: A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.