Abstract: A differential amplifier provides a high common mode rejection while maintaining substantially unchanged the input dynamic range. The differential amplifier includes a comparator having inputs to which are applied the two input signals, which are also applied to an operational amplifier, so that the comparator outputs a signal whose sign is indicative of the sign of the difference between the two input signals. The output of the operational amplifier is feedback to one of the inputs of the operational amplifier through a current mirror. This feedback signal is switched between the non-inverting input of the operational amplifier and the inverting input of the operational amplifier. The switching of the feedback signal ensures negative feedback, and is dependent upon the sign of the difference detected by the comparator.

Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).

Abstract: Fuzzy logic rules are applied to a method for indirectly measuring a physical signal to be monitored which would be difficult to directly measure. The measuring method comprises the steps of obtaining a derived physical signal from the physical signal to be monitored and measuring a value of the derived physical signal and its variations over time at suitably selected check points. A first set of fuzzy logic rules are applied to ascertain the presence or absence of an index signal adapted to mark at least first, second and third operational zones of the derived physical signal. Only the second operational zone is characterized by the presence of the index signal. First and second significant values of the physical signal to be monitored are measured as start and end values, respectively, of the second operational zone. An apparatus for indirectly measuring a physical signal is also disclosed.

Abstract: A charge pump circuit for integrated memory devices includes a plurality of stages cascade connected between an input terminal having a first voltage reference and an output terminal. Each stage includes a boost capacitor and one PMOS transistor functioning as a pass transistor. Each PMOS transistor has conduction terminals connected between the previous stage and the next stage, and a control terminal receiving a drive signal. The pass transistors are driven with a voltage that has a ground value when they are to be turned on, and a voltage equal to the highest of the positive voltages involved when they are to be turned off. The highest of the positive voltages involved is the output from the charge pump.

Abstract: An AC-coupled driver comprises a drain output stage in which the quiescent-state current is set by a current mirror, and by a bias current for the current mirror. The drain output stage includes a DC coupling connected to the current mirror by a capacitive-resistive network. The DC coupling allows the drain output stage to deliver a high current following input of an AC voltage signal into the AC-coupled driver.

Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

Abstract: An electronic circuit with suppression of high-voltage transients on the power supply line includes first and second power transistors series-connected between first and second power supplies, and first and second driving circuits for respective first and second power transistors. The first driving circuit includes a first diode and a first Zener diode, and the second driving circuit includes a second diode and a second Zener diode. Anodes of the first diode and the first Zener diode are connected to the cathode of the second Zener diode. A cathode of the first Zener diode is connected to the first power supply. A cathode of the first diode is connected to a gate of the first power transistor. Anodes of the second diode and the second Zener diode are connected together. A cathode of the second diode is connected to a gate of the second power transistor.

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node.

Abstract: The invention relates to a memory comprising memory cells arranged in continuous rows which are divided in at least two subrows separately selectable by a row decoder through respective word selection metallizations. Each word selection metallization extends over the row containing the corresponding subrow and the subrows of each row are interlaced.

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a cobalt film deposited on the polycrystalline silicon (4) and on the oxide layer (10). (FIG.

Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output signal that is supplied to another input of the comparator. The reference voltage signal reaches its steady operational value before the supply voltage, and the output signal has the same linear pattern as the supply voltage with a different angular coefficient. The comparator outputs a control signal for starting the first reading phase of the memory device. In one preferred embodiment, the memory device has a single power supply and a zero consumption standby mode. Additionally, there is provided a method for providing a first reading phase after a Power-On-Reset in a memory device.

Abstract: A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.

Abstract: A linear type of voltage regulator, having at least one input terminal adapted to receive a supply voltage and one output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driver circuit for the transistor. The driver circuit includes an operational amplifier having an input differential stage biased by a bias current which varies proportionally with the variations of the regulated output voltage at the output terminal of the regulator.

Abstract: An optical two-dimensional position sensor including a selective optical unit which faces, and is displaceable relative to, an integrated device. The selective optical unit is formed by a polarized light source and a filter with four quadrants which permits passage of light through two quadrants only. The selective optical unit is attached to a control lever such as to translate in a plane along a first direction and a second direction, and to pivot around an axis which is orthogonal to the preceding directions. In a transparent package, the integrated device comprises a first group of sensor elements which are spaced along the first direction, a second group of sensor elements which are spaced along the second direction and a third group of sensor elements which detect an angular position of the selective optical unit.

Abstract: An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.