Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.

Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

Abstract: A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dice, affixing a carrier to a front side of the plurality of integrated circuit dice, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.

Abstract: A voltage regulator includes two input pairs of opposite type transistors, p-type and n-type, to provide a soft-start functionality for gradually increasing the voltage regulator's output voltage from zero, or a voltage below the thresholds of the n-type transistors, to an operational voltage. The voltage regulator operates in a soft-start mode during which a variable input voltage signal is ramped up to allow the output voltage to reach the operational voltage, and a normal-operation mode during which the operational voltage is maintained.

Abstract: A current monitoring circuit includes: an output terminal configured to be coupled to a controller; an inverter having an output coupled to the output terminal; a first transconductance amplifier having first and second inputs configured to be coupled across a sense resistive element, and an output coupled to an input of the inverter; and a current generator having a second transconductance amplifier configured to generate a reference current at an output of the current generator based on a reference voltage, the output of the current generator being coupled to the input of the inverter, where the output of the inverter is configured to be in a first state when a load current flowing through the sense resistive element is higher than a predetermined threshold, and in a second state when the load current is lower than the predetermined threshold, and where the predetermined threshold is based on the reference current.

Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.

Abstract: A piezoelectric transducer includes a semiconductor body with a bottom electrode of conductive material. A piezoelectric element is on the bottom electrode. A first protective layer, on the bottom electrode and the piezoelectric element, has a first opening through which a portion of the piezoelectric element is exposed, and a second opening through which a portion of the bottom electrode is exposed. A conductive layer on the first protective layer and within the first and second openings is patterned to form a top electrode in electrical contact with the piezoelectric element at the first opening, a first biasing stripe in electrical contact with the top electrode, and a second biasing stripe in electrical contact with the bottom electrode at the second opening.

Abstract: A method of manufacturing an electronic module includes providing a base substrate having a first surface, providing a first supporting element having a first portion with an inclined top surface, and affixing the first supporting element to the first surface such that the inclined top surface is inclined with respect to the base substrate. A first reflector is coupled to the inclined top surface such that a rear surface of the first reflector is in physical contact with the inclined top surface of the first portion of the first supporting element, and a spacer structure is configured to form an interface for mounting lateral walls to the base substrate. A cap is positioned over and supported by the lateral walls to thereby define a chamber. The emitter, as well as a detector, are coupled to the first surface of the base substrate.

Abstract: A lens is positioned to be received by a lens holder. The lens includes a first electrical trace and the lens holder includes a second electrical trace. The first and second electrical traces form electrodes of a sense capacitor. A capacitance of the sense capacitor is sensed. From the sensed capacitance, a determination is made as to whether the lens is present and properly positioned in the lens holder.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: A MEMS device comprising a body, having a first surface and a second surface; a diaphragm cavity in the body extending from the second surface of the body; a deformable portion in the body between the first surface and the diaphragm cavity; and a piezoelectric actuator, extending on the first surface of the body, over the deformable portion. The MEMS device is characterized in that it comprises a recess structure extending in the body and delimiting a stopper portion for the deformable portion.

Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

Abstract: A ToF sensor includes an array of pixels having first and second subsets of pixels, first and second pluralities of TDCs, a routing bus having first and second pluralities of bus drivers, and a controller configured to: when the first subset of pixels is active and the second subset of pixels is not active, control the first plurality of bus drivers to route events from half of the pixels of the first subset to the first plurality of TDCs and control the first and second pluralities of bus drivers to route events from the other half of the pixels of the first subset to the second plurality of TDCs, and when the first subset of pixels is not active and the second subset of pixels is active, control the first plurality of bus drivers to route events from the second subset of pixels to the first plurality of TDCs.

Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.