Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract: A computing system includes a first hardware element having a first accelerometer and a first gyroscope, and a second hardware element having a second accelerometer and a second gyroscope. The first and second hardware elements are moveable with respect to each other. The computing system recursively generates a result signal indicative of a relative orientation of the first and second hardware elements with respect to each other. The result signal may be generated by generating a first intermediate signal indicative of a angle between the first and second hardware elements based on signals generated by the first and second accelerometers and generating a second intermediate signal indicative of the angle based on signals generated by the first and second gyroscopes. The result signal indicative of the angle may be generated as a weighted sum of the first intermediate signal and the second intermediate signal. At least one of the first and second hardware elements is controlled by on the result signal.

Abstract: Hall sensing signals are received in a spinning readout pattern of subsequent readout phases, wherein the pattern is cyclically repeated at a spinning frequency and a polarity of the Hall sensor signals is reversed in two non-adjacent readout phases of the readout pattern. A signal storage circuit includes signal storage capacitors. An accumulation circuit includes accumulation capacitors. A switch network is selectively actuated to couple the signal storage capacitors with the accumulation capacitors synchronously with phases in the spinning readout pattern in subsequent alternating first and second periods. The spinning output is stored with alternating opposite signs on the signal storage capacitors and the Hall sensing signals are stored in the signal storage capacitors and then accumulated on the accumulation capacitors with alternate signs in subsequent periods. The accumulated output signal is then demodulated with a demodulation frequency half the spinning frequency.

Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

Abstract: Described herein is a method including measuring a current in a wire, normalizing the measured current, and comparing the normalized measured current to a control curve. The control curve is a function of a series of normalized current magnitudes and reaction times for corresponding ones of that series of normalized current magnitudes. The method further includes limiting the current in the wire based upon the comparison. The reaction times for ones of the series of normalized current magnitudes are times at which current limitation would occur if the normalized current remained at an associated normalized current magnitude.

Abstract: In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.

Abstract: A system includes a mirror controller driving fast and slow axis mirrors of a projector with fast and slow axis drive signals to reflect a collimated light beam in a scan pattern across the target. The scan pattern includes trace lines which cause display of an input video stream on the target, and retrace lines which operate to return the slow axis mirror to a proper location to begin a next frame of the scan pattern. The slow axis drive signal is generated to maintain a number of trace lines in each frame of the scan pattern constant across frames, but the slow axis drive signal is modified to lock a phase and frequency of the displayed video to a phase and frequency of the input video stream by changing a number of retrace lines in each frame of the scan pattern on a frame-by-frame basis by a non-integer number.

Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.

Abstract: A first Radio-Frequency-to-Direct-Current (RF2DC) transducer receives a first signal from a sensing antenna and generates energy stored by an energy storage circuit. An energy transfer circuit is controllably switched between an energy storage state where energy is stored in the energy storage state and an energy transfer state where stored energy is transferred to a load. The voltage at the energy storage circuit is alternatively variable between an upper value and a lower value around a voltage setting point. A second RF2DC transducer, which is a down-scaled replica of the first RF2DC transducer, produces a second signal indicative of an open-circuit voltage of the first RF2DC transducer. The voltage setting point is set as a function of the second signal indicative of the open-circuit voltage of the first RF2DC transducer.

Abstract: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

Abstract: A microelectromechanical pressure sensor includes a monolithic body of semiconductor material having a front surface. A sensing structure is integrated in the monolithic body and has a buried cavity completely contained within the monolithic body at the front surface. A sensing membrane is suspended above the buried cavity and is formed by a surface portion of the monolithic body. Sensing elements of a piezoresistive type are arranged in the sensing membrane to detect a deformation of the sensing membrane as a result of a pressure. The pressure sensor is further provided with a self-test structure integrated within the monolithic body to cause application of a testing deformation of the sensing membrane in order to verify proper operation of the sensing structure.

Abstract: A semiconductor device includes a strain gauge on a substrate, the strain gauge configured to measure a stress of the substrate; and a temperature sensor disposed within the substrate, the temperature sensor being decoupled from the stress of the substrate.

Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.

Abstract: A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

Abstract: An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.

Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.

Abstract: A pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply through a quenching element, with the SPAD having a capacitance at its anode formed from a deep trench isolation, with the quenching element having a sufficiently high resistance such that the capacitance is not fully charged when the SPAD is struck by an incoming photon. The pixel includes a clamp transistor configured to be controlled by a voltage clamp control signal to clamp voltage at an anode of the SPAD when the SPAD is struck by an incoming photon to be no more than a threshold clamped anode voltage, and readout circuitry coupled to receive the clamped anode voltage from the clamp transistor and to generate a pixel output therefrom. The threshold clamped anode voltage is below a maximum operating voltage rating of transistors forming the readout circuitry.

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.